帳號:guest(3.12.163.124)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):陳在煌
作者(外文):Chen. Tsai Huang
論文名稱(中文):即時偵測測試機台異常之雲端測試良率監控與分析方法
論文名稱(外文):Real-Time Abnormality Detection of Automatic Test Equipment by Cloud-Based Test Yield Monitoring and Analysis
指導教授(中文):吳誠文
指導教授(外文):Wu, Cheng Wen
口試委員(中文):李昆忠
黃俊郎
洪浩喬
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:102061629
出版年(民國):105
畢業學年度:104
語文別:英文
論文頁數:66
中文關鍵詞:自動化測試機台良率分析
外文關鍵詞:automatic test equipmentyield analysis
相關次數:
  • 推薦推薦:0
  • 點閱點閱:605
  • 評分評分:*****
  • 下載下載:5
  • 收藏收藏:0
為了因應現今半導體製造業大量量產的需求,能夠快速測試大量半導體產品的自動化測試機台被大量使用在量產過程中的測試環節。然而在測試過程中,某些硬體問題會導致測試的誤判,並引起真實良率和測試良率之間的差異。此問題若發生,將使整批產品必須被重新測試,耗費大量的時間成本。本研究提出一個在量產過程中,即時偵測測試機台硬體問題的方法,以節省重新測試的時間。我們提出名為“自動化測試設備異常偵測器”的工具程式,此工具會在量產測試過程中,即時偵測各測試設備上之測試良率。若測試良率中有異常狀況,表示有測試設備之硬體異常發生,偵測器偵測到異常狀況後會發出一個警告訊息,以提示使用者有關此測試良率異常。經過驗證,證明了此偵測器有能力觀測到測試良率中的異常現象,從而發現測試設備中是否有硬體問題產生;使用者得以及時暫停測試,並嘗試修復測試設備中的硬體異常,並且節省重新測試所需要的大量時間。
An automatic test equipment (ATE) is developed to test the numerous integrated circuits (ICs) automatically. Some ATE issues occur during the testing and lead to the difference of the true yield and the test yield. It is a waste of time to re-test the whole lot of ICs if the deviation of yield caused by an ATE issue occurs during the testing. A method of detecting the ATE issues in real-time is proposed for saving the re-test time. A data analyzer called ATE Variance Detector (ATEVD) monitors the test yield in the data that upload from the ATEs. If an abnormality of test yield exists in the test data, the ATEVD notifies the engineer about the abnormality. We established a web server that contains the ATEVD and a data generator, which is developed to generate the test data of the ATEs. We verified the ATEVD of the ability to detect the abnormality of the test yield in the test data, and proved that the ATEVD is able to detect the ATE issue through monitoring the test data. We also give the experiments about how the detection rule settings affect the detection properties. Finally, we proved that the ATEVD is able to detect the abnormality of the test yield by monitoring the test data in a short time after the ATE issue occurs. Therefore, the engineer that noticed of the ATE issues is able to halt the testing and fix the ATE issues. A great deal of re-testing time is hence saved.
Abstract i
Contents ii
List of Figures iv
List of Tables vi
Chapter 1 Introduction 1
Chapter 2 Background and Related Works 4
2.1 Basics of ATE 4
2.1.1 The Concept of Testing 4
2.1.2 Basic Operations of a Test Item 6
2.1.3 The Overall Test Flow 7
2.1.4 Automatic Test Equipment 9
2.2 ATE Parameters Variance Phenomenon 12
2.2.1 Comparison Circuit 12
2.2.2 Variance Phenomenon 13
2.3 Assumptions 15
Chapter 3 Detection Algorithm 17
3.1 Variance between Time Zones 17
3.2 Variance among Different ATEs 19
3.3 Variance among Sites 22
3.4 Burst Failures 23
3.5 The Detection Flow 25
Chapter 4 System Implementation 28
Chapter 5 Simulation and Verification 31
5.1 Simulation Implementation 31
5.1.1 The Data Generator 32
5.1.2 The Database 34
5.2 Verification 42
5.2.1 Variance between Time Zones Detection Capability Verification 43
5.2.2 Variance among Different ATEs Detection Capability Verification 44
5.2.3 Variance among Different Sites Detection Capability Verification 46
5.2.4 The Efficiency of Burst Failure Detection 48
5.3 The Influence of the Detection Rule Settings 49
5.3.1 Math Calculation 50
5.3.2 Threshold and Sample Size Versus Detection Accuracy and Analysis 52
5.3.3 Threshold and Sample Size Versus Detection Efficiency 57
5.3.4 The Reason of Misdetection and False Alerts 59
5.3.5 Summary 61
Chapter 6 Conclusions and Future Work 63
6.1 Conclusions 63
6.2 Future Work 63
Bibliography 65
[1] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures, Elsevier (Morgan Kaufmann), San Francisco, 2006.
[2] K. Brindley, Automatic Test Equipment, USA: Elsevier, 2013.
[3] A. Grochowski, D. Bhattacharya, T. R. Viswanathan, and K. Laker, "Integrated Circuit Testing for Quality Assurance in Manufacturing: History, Current Status, and Future Trends", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 44, Issue: 8, Aug. 1997, pp. 610-633.
[4] H.-J. Wang, C.-F. Chien, C.-J. Kuo, "Analyzing Alternative Strategies of Semiconductor Final Testing", in Multi-Objective Programming and Goal Programming: Theory and Applications, Eds. T. Tanino, T. Tanaka, and M. Inuiguchi, Springer, 2003, pp. 409-414.
[5] M. Ishida, T. Kusaka, T. Nakura, S. Komatsu, and K. Asada, "Statistical Silicon Results of Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills", in Proc. 2014 IEEE International Test Conference (ITC), Oct. 2014, pp. 1-10
[6] J. Wang, D. M. H. Walker, A. Majhi, B. Kruseman, G. Gronthoud, L. E. Villagra, P. van de Wiel, and S. Eichenberger, "Power Supply Noise in Delay Testing", in Proc. 2006 IEEE International Test Conference (ITC), Oct. 2006, pp. 1-10.
[7] C.-F. Chien, and J.-Z. Wu, "Analyzing Repair Decisions in the Site Imbalance Problem of Semiconductor Test Machines", IEEE Transactions on Semiconductor Manufacturing, Vol. 16, Issue: 8, Nov. 2003, pp. 704-711.
[8] J. Aerts, E. J. Marinissen, "Scan chain design for test time reduction in core-based ICs, " in Proc. IEEE International Test Conference (ITC), Washington, DC, Oct. 1998, pp. 448-457.
[9] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B.Courtois, " Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers", IEEE Transactions on Computers, Vol. 44, Issue: 2, Feb. 1995, pp. 223-233.
[10] P. P. Fasang, W. F. Bridgewater, “Built-in self test for integrated circuit memory,” U.S. Patent 5,138,619, Feb. 15, 1990.
[11] J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, "Processor-based Built-In Self-Test for Embedded DRAM", IEEE Journal of Solid-State Circuits, Vol. 33, Issue: 11, Nov. 1998, pp. 1731-1740.
[12] E. J. McCluskey, "Built-In Self-Test Techniques", IEEE Design & Test of Computers, Vol. 2, Issue: 2, Apr. 1985, pp. 21-28.
[13] S. Cherubal, A. Chatterjee, "Optimal INL/DNL Testing of A/D Converters Using a Linear Model," in Proc. IEEE International Test Conference (ITC), Atlantic City, Oct. 2000, pp. 358-366.
[14] J. Doemberg, H.-S. Lee, D. Hodges, "Full-Speed Testing of A/D Converters", IEEE Journal of Solid-State Circuits, Vol. 19, Issue: 6, Dec. 1984, pp 820-827.
[15] G. Perry, The Fundamentals of Digital Semiconductor Testing, Version 3.2. Los Gatos, Calif., USA: Soft Test Inc., 2003.
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *