由於靜態隨機存取記憶體具有快速存取的記憶功能，因此在電子產品中是一
個非常重要的電路。它的容量是影響整個系統速度的主要因素。為了達到大量存
取資料的需求，此記憶體在整個系統所佔的面積越來越大。因此，如何降低功率消耗是一個非常重要的議題。
為了降低靜態隨機存取記憶體的功率消耗，降低供給電壓是最直接且有效的方式，然而，靜態隨機存取記憶體操作在低電壓時將會面臨以下的問題：（1）於寫入操作時會導致寫入失敗（2）於讀取操作時會產生讀取擾動（3）於寫入操作時會產生半選擇擾動。先前的作品提出了一個創新的記憶胞搭配雙向分離控制技術，此作品架構是將字組線分成字組線Ｌ和字組線Ｒ，以及將接地端分成接地端Ｌ和接地端Ｒ。其操作特色為偽單邊寫入於兩相位中，單邊讀取於單相位中。此記憶胞藉由抬升接地端的電壓來改善讀取擾動和半選擇擾動的問題。然而，根據記憶胞矩陣的佈局以及資料格局的方式，分別會產生接地彈跳與抬升接地端電壓不穩定的問題。
針對接地彈跳的問題，我們採用前人提出的方式解決，稱之為陣列邊緣記憶體技術。針對另一個議題，此作品提出了雙階段電荷分享機制。根據不同的資料格局會使接地端所看到的負載有所不同，而為了達到低功耗的需求，採用電荷分享的方式，第一步驟先將電路的電壓重置，第二步驟會做第一次的電荷分享決定接地端的電壓，第三步驟則會去偵測此電壓的高低決定是否需要再做第二次的抬升，以達到較好的記憶胞性能。
透過六十五奈米互補式金氧半邏輯製程技術，建構出一容量為四千字元之創新記憶胞搭配雙向分離控制電路，藉由示波器的量測，此作品可達到的最低操作電壓為400毫伏特，此外，和沒有抬升接地端電壓的情況下做比較，最低操作電壓的改善為120毫伏特。

Static Random Access Memory (SRAM) is an important circuit in the electronic products owing to the function of high-speed memory. It’s capacity is the main reason for affecting the speed of systems. In order to meet the substantial requirements of stored data, it occupies more and more area in the systems. Hence, the power consumption of SRAM becomes an indispensable issue.
To reduce power consumption of SRAM, lowering the supply voltage is a direct and effective way. Nevertheless, SRAM operating at low VDD would suffer from the following issue : (1) write failure in write operation (2) read disturb in read operation (3) half-select disturb in write operation. Previous work proposes a novel 6T cell with dual-split control (DSC) technique. The word-line (WL) of cell is divided into WLL and WLR. Also, the ground (CVSS) of cell is divided into CVSSL and CVSSR. The feature of cell is pseudo single-ended write with two phases and single-ended read with one phase. It can improve read disturb and half-select disturb by raising CVSS. However, according to the layout and data pattern of cell array, it suffers from ground bounce and the difficulty for raising CVSS.
For ground bounce, we adopt the method proposed by pervious work which is called array-edge memory (AEM) technique. For the other issue, we propose two step charge sharing scheme. In accordance with the data pattern of cell array, loading of CVSS would be different. For the requirement of low power, we employ charge sharing approach. The first step is reset state. At the second step we do the first charge sharing to generate the voltage of CVSS. At the third step, we detect this voltage to decide whether it should be raised again to achieve better performance of cell.
Based on 65nm CMOS logic process, we fabricate a 4Kb SRAM composed of 6T cell with DSC scheme. This work achieves VDDmin equal to 400mV through oscilloscope testing. In addition, VDDmin improvement is 120mV compared with no raising for CVSS.

摘要 i
Abstract iii
Contents v
List of Figures viii
List of Tables x
Chapter 1 Introduction 1
1.1 SRAM Background 1
1.2 About MOSFET Current Model at Low Voltage 5
1.3 Overview of the Thesis 6
Chapter 2 Introduction of SRAM from Architecture 8
2.1 Basic Concept of Conventional 6T SRAM 8
2.2 Write Operation 10
2.3 Read Operation 11
2.4 Standby Operation 12
2.5 Structure of Conventional 6T SRAM 13
Chapter 3 Issue of Low Voltage 6T SRAM Cell 16
3.1 Introduction of 6T SRAM Cell 16
3.1.1 Write Operation 18
3.1.2 Read Operation 19
3.2 Process Variation 19
3.3 Write Failure in Write Operation 20
3.4 Read Disturb in Read Operation 21
3.5 Half-Select (HS) Disturb in Write Operation 22
3.6 Analyses of Conventional 6T Cell Design 23
3.6.1 Write Margin (WM) 23
3.6.2 Static Noise Margin (SNM) For Read (RSNM) and Hold (HSNM) 24
Chapter 4 Design Challenge of Dual-Split Control (DSC) 6T SRAM at low Voltage 26
4.1 Background 26
4.2 Operation 30
4.2.1 Write Operation 30
4.2.2 Read Operation 32
4.3 Issue of Ground Bounce 33
4.4 Issue of Cell VSS (CVSS) Raising 34
4.5 Impact of CVSS Raising Voltage Level 35
4.5.1 WM Analysis 36
4.5.2 RSNM Analysis 37
4.5.3 HSNM Analysis 38
4.5.4 Summary for SNM 39
Chapter 5 Proposed Two Step Charge Sharing Scheme 41
5.1 Concept 41
5.2 Operation Step 42
5.3 Error Code Detector Introduction 45
5.4 Analysis 47
5.4.1 CVSS Raising Voltage Level 47
5.4.2 Cell VDDmin 48
Chapter 6 DSC 6T SRAM Macro Implementation 50
6.1 Floor Plan of SRAM Macro 50
6.2 Design for Test Chip 52
6.3 Die Photo of SRAM Macro 53
Chapter 7 Experimental Result and Conclusion 54
7.1 Chip Performance Measurement 54
7.2 Summary and Conclusion of Thesis 56
Reference 59

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