摘要
隨著近年來對於消費性電子產品不斷成長的需求，非揮發性記憶體的需求也跟著不斷增加，而目前市場上常見的快閃記憶體，為主要的大容量非揮發儲存記憶體，然而隨著製程技術持續演進，快閃記憶體在製程微縮之下，面臨了許多挑戰。因此，下一世代嶄新的非揮發性記憶體也就成為了取代快閃記憶體的解決方案。

在許多研究當中，非揮發性電阻式記憶體(RRAM)是一個極有潛力的解決裝置，利用高組態與低組態來儲存資料，主要優點具有CMOS邏輯製程的相容性、較小的單位面積與較低的寫入功耗.而在最新的架構當中，電阻式記憶體更可以藉由三維堆疊來進一步增加記憶細胞的密度，然而，不論是在電阻式記憶體本身的阻值飄移或是三維結構所造成的潛行電流都可能會造成在讀取上良率的降低，而且潛行電流的大小會隨著陣列加大而更加嚴重，還會與先前已存在陣列的資料相關，因此在應用上仍有所限制。

我們所提出的感測電路主要先偵測背景的潛行電流，藉由電路運作後來消除因為潛行電流所造成的讀取電壓偏移，之後也會利用特殊的參考電壓選取來更加進一步的放大讀取感測範圍。

我們將感測電路實作在65奈米的12Kb 記憶體測試晶片，在正常電壓操作之下，可以在潛行電流為19微安培，仍然讀取出正確的值，達到成功驗證機制的目的。

Abstract
Due to the growing demand of consumer electronics in recent years, demand of non-volatile memories continues to grow up. The most common large capacity memory is Flash. However, as the technology process advances, Flash memory has many challenges in process scaling. Therefore, next generation emerging non-volatile memory has become the replacement solution for Flash memory.
In many researches, non-volatile resistive random access memory (RRAM) is a prominent solution device. It stores data by its high resistance state and low resistance state. Its advantages include CMOS-logic compatibility, small area size and low write power consumption. In the latest array structure, 3D stacking can further increase the density of RRAM. Nonetheless, either the resistance variation of RRAM or the sneak current of 3D RRAM structure can decrease the reading yield. The sneak current issue gets worse when array size continues to be large and it is also data-dependent.
Our proposed sensing scheme mainly detects the background sneak current and eliminates the voltage offset due to sneak current. We also choose a special reference voltage to enlarge sensing margin .
We implemented the sensing scheme in 65nm 12kb test chip. In normal VDD operation, correct data can be read out even sneak current is over 19uA. The voltage offset due to sneak current cancellation function can be verified in this chip.

Contents
摘要 i
Abstract ii
Contents iv
List of Figures v
List of Tables viii
Chapter 1 Introduction 1
1.1 Memory Landscape 1
1.1.1 Read Only Memory 4
1.1.2 Programmable NVMs 4
1.2 Challenges of Flash Memory in Advanced Technology 6
1.3 Emerging Non-Volatile Memories 8
Chapter 2 Characteristic of Via-RRAM 12
2.1 Structure of Via-RRAM 12
2.2 Switching Mechanism 13
2.3 Write Operation 15
2.4 Distribution of Via-RRAM 16
2.5 3D array structure of Via-RRAM 17
Chapter 3 Design Challenges of 3D Via-RRAM 19
3.1 Design Challenge 19
3.1.1 3D Cross-Point Via-RRAM Structure Read Issue 19
3.2 Previous Arts 21
3.2.1 Conventional Latch-Type Voltage Sense Amplifier 21
3.3 Proposed Sense Amplifier 23
3.3.1 Concept of Proposed Sensing Amplifier Scheme 23
3.3.2 Operation of Proposed Sensing scheme 28
3.3.3 VREF Generation of Proposed Sensing Scheme 40
3.4 Analysis and Comparison 43
3.4.1 Sneak current voltage offset cancellation 43
3.4.2 Sneak in different array sizes 44
3.4.3 Sensing Margin Enlargement 45
Chapter 4 Measurement Results and Conclusion 46
4.1 3D Cross-Point Via-RRAM Test mode Macro 46
4.2 Design for Test Chip 48
4.3 Measured Performance 49
4.4 Performance Measurement 51
4.5 Conclusions and Future Work 55
Reference 56

[1] Dong Uk Lee, et al., "25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV," Solid-State Circuits Conference Digest of Technical Papers, 2014 IEEE International , vol., no., pp.432,433, 9-13 Feb. 2014
[2] IC Insights, “Total Flash Memory Market Will Surpass DRAM for First Time in 2012”, http://www.icinsights.com/data/articles/documents/485.pdf
[3] P. Pavan, et al., "Flash memory cells-an overview," Proceedings of the IEEE , vol.85, no.8, pp.1248,1271, Aug 1997
[4] R. Bez, et al., "Introduction to flash memory," Proceedings of the IEEE , vol.91, no.4, pp.489,502, April 2003
[5] C. Villa, et al., "A 125 MHz burst-mode flexible read-while-write 256 Mbit 2b/c 1.8V NOR flash memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, vol. 1, pp. 52-584, Feb. 2005.
[6] M.-F. Chang, et al., "A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme," IEEE Journal of Solid-State Circuits, vol. 44, pp. 987-994, March 2009.
[7] J. Javanifard, et al., "A 45nm Self-Aligned-Contact Process 1Gb NOR Flash with 5MB/s Program Speed," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 424-624, Feb. 2008.
[8] C. Gerardi, et al., "Performance and reliability of a 4Mb Si nanocrystal NOR Flash memory with optimized 1T memory cells," IEEE International Electron Devices Meeting (IEDM), pp. 1-4, Dec. 2008.
[9] T. Ogura, et al., "A Fast Rewritable 90nm 512Mb NOR “B4-Flash” Memory with 8F2 Cell Size," Symposium on VLSI Circuits, pp. 198-199, June 2011.
[10] Hang-Ting Lue, et al., "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device," Symposium on VLSI Technology, pp. 131-132, June 2010.
[11] Chih-Ping Chen, et al., " A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)," Symposium on VLSI Technology, pp. 91-92, June 2012.
[12] Hang-Ting Lue, et al., "A Novel Bit Alterable 3D NAND Flash Using Junction-free P-channel Device with Band-to-Band Tunneling Induced Hot-Electron Programming," Symposium on VLSI Technology, pp. T152-T153, June 2013.
[13] Ki-Tae Park, et al., "Three-dimensional 128Gb MLC vertical NAND Flash-memory with 24-WL stacked layers and 50MB/s high-speed programming," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 334-335, Feb. 2014.
[14] R. Cernea, et al., "A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 420-624, Feb. 2008.
[15] Choong-Ho Lee, et al., "A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory," IEEE International Electron Devices Meeting (IEDM), pp. 5.1.1-5.1.4, Dec. 2010.
[16] IC Insights, “Total Flash Memory Market Will Surpass DRAM for First Time in 2012”, http://www.icinsights.com/data/articles/documents/485.pdf
[17] Y. Koh, "NAND Flash Scaling Beyond 20nm," IEEE International Memory Workshop, pp. 1-3, May 2009.
[18] Z. Wei, et al., "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism," IEEE International Electron Devices Meeting (IEDM), pp. 1-4, Dec. 2008.
[19] K. Prall, "Scaling Non-Volatile Memory Below 30nm," IEEE Non-Volatile Semiconductor Memory Workshop, pp. 5-10, Aug. 2007.
[20] S. Lee, "Scaling Challenges in NAND Flash Device toward 10nm Technology," IEEE International Memory Workshop, pp. 1-4, May 2012.
[21] D. Gogl, et al., "A 16-Mb MRAM featuring bootstrapped write drivers," IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 902-908, 2005.
[22] G. De Sandre, et al., "A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 268-269, 2010.
[23] D.Takashima, et al., "A 100MHz ladder FeRAM design with capacitance-coupled-bitline cell," IEEE Symposium on VLSI Circuits, pp. 227-228, 2010.
[24] Sheu Shyh-Shyuan, et al., "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 200-202, 2011.
[25] R. Takemura, et al., "A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme," IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 869-879, 2010.
[26] J. J. Nahas, et al., "A 180 Kbit Embeddable MRAM Memory Module," IEEE Journal of Solid-State Circuits, vol. 43, no. 8, pp. 1826-1834, 2008.
[27] F. Bedeschi, et al., "A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage," IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 217-227, 2009.
[28] A. Sheikholeslami and P. G. Gulak, "A survey of circuit innovations in ferroelectric random-access memories," Proceedings of the IEEE, vol. 88, no. 5, pp. 667-689, 2000
[29] R. Ogiwara, et al., "A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor," IEEE Journal of Solid-State Circuits, vol. 35, no. 4, pp. 545-551, 2000.
[30] Min-Che Hsieh, et al., " Ultra high density 3D via RRAM in pure 28nm CMOS process," IEEE International Electron Devices Meeting (IEDM), pp. 10.3.1-10.3.4, Dec. 2013.
[31] Yu-Cheng Liao, et al., " Via Diode in Cu Backend Process for 3D Cross-Point RRAM Arrays," IEEE Journal of the Electron Devices Society, pp. 149-153, Nov. 2014.
[32] C. Cagli, et al., "Evidence for threshold switching in the set process of NiO-based ReRAM and physical modeling for set, reset, retention and disturb prediction," IEEE International Electron Devices Meeting Dig. Tech. Papers, pp. 1-4, 2008
[33] C.J. Chevallier, et al., "A 0.13µm 64Mb multi-layered conductive metal-oxide memory," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 260-261, Feb. 2010.
[34] E. Ou, et al., "Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory," IEEE Journal of Solid-State Circuits, pp. 2158-2170, Sept. 2011.
[35] A. Kawahara, et al., "An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 432-434, Feb. 2012.
[36] Tz-yi Liu, et al., "A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology," IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 210-211, Feb. 2013.
[37] B. Wicht, et al., "Yield and speed optimization of a latch-type voltage sense amplifier," IEEE Journal of Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, 2004.
[38] Xiaoyong Xue, et al., " A 0.13 µm 8 Mb Logic-Based CuxSiy O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction," IEEE Journal of Solid-State Circuits, pp. 1315-1322, May. 2013.
[39] Y. L. Song, et al., " Reliability significant improvement of resistive switching memory by dynamic self-adaptive write method," IEEE VLSI Technology (VLSIT), 2013 Symposium on, pp. T102 - T103, June. 2013.