在有限電能裝置的晶片中 (如手機、可攜式產品、物聯網)，通常需要動態調整電源，甚至進行部分晶片的關機程序以降低待機耗能。現存大多方法使用靜態隨機存取記憶體(SRAM) 用於快速計算，並另外使用非揮發性記憶體（NVM）為斷電資料存儲。然而，這種採用兩個晶片組的方式（SRAM + NVM 2-macro solution）受到晶片的傳輸介面限制，造成資料備份時間過長和消耗大量的傳輸能量。非揮發性靜態隨機存取式記憶體(nvSRAM)以位元對位元的平行方式傳輸資料，使得資料備份及資料復元不需經過傳輸介面，達到儲存時間更短、更省能，對可攜式裝置而言是個更好的選擇。
這項研究提出了使用七顆電晶體和一個憶阻器組成的非揮發性靜態隨機存取式記憶體來達到1）通過使用單一的NVM器件減少儲存能量，2）透過使用脈衝重寫操作（POW）抑制恢復期間直流短路電流，和3）透過差異提供初始化（DSI）實現高恢復良率。這個初始化並覆寫（IOW）的操作相比以前的nvSRAM提高了盈虧平衡時間（BET）6+X倍。我們使用氧化鉿憶阻式記憶體和90nm工藝製造的16Kb的IOW-7T1R nvSRAM。這代表了有史以來第一實作個驗證的單-NVM nvSRAM晶片。在測試模式下獲得的測量結果證實，所提出的NVSRAM和傳統使用2R的nvSRAM減少2倍儲存耗能和94X恢復恢復耗能。

Energy-efficient chips, such as wearable and IoT devices, employ SRAM for computing and nonvolatile memory (NVM) for power-off storage to reduce standby current. Unfortunately, this 2-macro (SRAM+NVM) scheme cannot achieve frequent power-off and short BET against SRAM at sleep-mode using a low supply-voltage (VDD), due to large energy usage and slow store (power-off) and restore (power-on) operations, caused by the word-by-word serial transfer of data.
Nonvolatile SRAMs (nvSRAM), which perform bit-to-bit data transfer between SRAM and NVM devices within a single cell, are capable of block-level parallel data transfer with faster store/restore operations than are 2-macro schemes.
This study proposes a 7T1R nonvolatile SRAM (nvSRAM) to 1) reduce store energy by using a single NVM device, 2) suppress DC-short current during restore operations through the use of a pulsed-overwrite (POW) scheme, and 3) achieves high restore yield by using a differentially supplied initialization (DSI) scheme. This initialization-and-overwrite (IOW) 7T1R nvSRAM improves breakeven-time (BET) by 6+x, compared to previous nvSRAMs. We fabricated a 16Kb IOW-7T1R nvSRAM using HfOx RRAM and a 90nm process. This represents the first ever silicon verified single-NVM nvSRAM macro. Measurements obtained in test-mode confirm that the proposed nvsRAM reduces store energy by 2x and restore energy by 94x, compared to 2R-based nvSRAMs.

Content
中文摘要 II
Abstract IV
1. Intro 1
1.1 Memories in Modern Processes 1
1.2 Two-Macro Memory solution 2
1.3 Non-volatile SRAM (nvSRAM) 3
2 Emerging Memories 5
2.1 PCM 6
2.2 MRAM 7
2.3 FeRAM 9
2.4 RRAM 10
3. Previous Works 12
3.1 Device Operations 12
3.2 6T2R Cell 15
3.3 8T2R nvSRAM Cell 17
3.4 4T2R MRAM Cell 19
3.5 Rnv8T Cell 21
4. This Work 22
4.1 Cell Structure 23
4.2 Store operation 24
4.2A Bipolar Cell 24
4.2B Unipolar Cell 25
4.3 Restore Operation 26
4.3A Dual supply Initialization (DSI) 26
4.3B Pulse Overwrite (POW) 27
4.4 SRAM Mode Operation 28
5. Analysis 28
5.1 Yield 29
5.2 Energy 29
5.3 WM 32
5.4 Chip-level restore 33
5.5 Restore without Power-down 34
6. Implementation and measurement results 35
6.1 Test Mode Design 35
6.2 Measured Results 37
7. Summary 40
7.1 Future Works 42
References 43

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