隨著晶片電路設計的複雜度與晶片的面積越來越大，時脈網路在任何的同步電路系統中佔有越來越重要的地位。尤其是在三維積體電路的製造產業中，時脈網路的設計與測試方法都是相當不容易的。即使是一些在時脈網路上的微小瑕疵，都可能為整個系統帶來災難性且不可挽回的傷害。因此在晶片製造的出廠前測試與功能性的測試都是非常重要的一環，以上兩種測試都是用來預防這些傷害。在這份研究裡，我們提出一個利用級距概念的方法，對時脈網路上的微小時脈延遲錯誤進行偵測，並且也裝備有可調式單一脈衝產生器，產生測試所需的時脈訊號與測試樣本訊號，再將以上兩種訊號送入待測目標電路進行測試。該可調式單一脈衝產生器是利用台灣積體電路製造股份有限公司的九十奈米互補式金屬氧化物半導體製程，並且整個電路都只使用標準式細胞電路完成設計。利用我們所提出的測試方法，我們可以透過外部的分析，診斷出受到延遲錯誤影響的正反器。此測試方法，使得測試過程是容易執行的，執行測試的方式如同一般的沖刷測試，並且此測試方法不需要更改待測目標電路的時脈網路，因此，在我們所提出的測試方法下，並不會帶給待測目標電路的時脈網路額外的負擔，另外在對於不同的目標待測電路時，我們也不需要更換測試的樣本訊號。

As the chip design is more complex and larger size, the clock network is also more critical in any synchronous system. In 3-D IC, it is especially difficult to design and test. Even though a small fault at the clock network, it could lead catastrophic failure to damage the system. Therefore, it is important to detect in the manufacturing test or functional test to prevent this failure. In this work, we propose a test method with bin concept to detect the small clock delay fault at clock network, and also equip with the Tunable One-Shot Pulse Generator to generate the test clock and test pattern to feed the circuit under test. The Tunable One-Shot Pulse Generator is designed in TSMC 90nm CMOS process using only standard cells. By this test method, we can diagnosis the faulty flip-flop which is affected by clock delay fault through the outlier analysis. It is easy in the procedure to execute test as like flush test, and the method does not modify the clock network of the circuit under test. Consequently, the test process will not bring the loading to the clock network of the circuit under test, and we does not need to change the test pattern for the different circuit under test.

Abstract i
摘要 ii
致謝 iii
Content iv
List of Figures vi
List of Tables viii
Chapter 1 Introduction 1
1.1 Background and Motivation 1
1.2 Thesis Organization 4
Chapter 2 Preliminaries 5
2.1 Different Pulse-Width of Test Clock 5
2.2 Review of Scan-Excite-Scan Flush Test (SES-Flush Test) 7
Chapter 3 Proposed Methodology 10
3.1 Overview 10
Chapter 4 Architecture and Operation 13
4.1 Operation Sequence 13
4.2 Architecture of Test Clock Generator 14
4.3 All-Digital Phase-Locked Loop (ADPLL) 16
4.4 Tunable Short Pulse Block in Test Window 16
4.4.1 Coarse-Shrinking Block 18
4.4.2 Fine-Shrinking Block 19
4.5 Calibration in Initial State 23
Chapter 5 Experimental Results 26
5.1 Tunable One-Shot Pulse Generator 26
5.1.1 Short-pulse-width 26
5.1.2 Chip layout 28
5.1.3 Characteristic Table 29
5.2 Fault Free 〖PB〗_min Range 29
5.2.1 Fault injection in Benchmark Circuit 32
5.2.2 Sweeping-Test with CDF Injection 33
5.3 Testing Time 37
Chapter 6 Conclusion 38
References 39

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