由於成本效益比靜態隨機存取記憶體高以及隨機存取速度比快閃記憶體更為快速的優點，嵌入式動態隨機存取記憶體被廣泛應用於多數的電子產品當中。然而對於系統單晶片而言，持續上升的功率消耗是一個存在的大問題。因此低功率消耗的研究議題應該要被考慮到晶片設計當中。對於內嵌式動態隨機存取記憶體而言，利用傳統制訂的自我刷新週期是為了要確保已經寫入的資料能夠被完整地保存於記憶胞陣列當中。但是如果要在低壓操作，記憶胞的資料保存時間將會比高壓環境下的保存時間要能減少許多。因此在低壓的情況下，利用傳統的自我刷新週期將要更快速的刷新而產生額外的資料保存功率消耗。
為了能夠操作在更低壓的環境下，我們提出了低壓感測及回寫機制的放大器有效地去延長記憶胞的資料保存時間。藉由操作在回寫機制，將資料提升至更高的電位，以至於在感測階段裕度增強，達成在低壓操作可以成功讀取資料，並且降低在自我刷新週期所消耗的功率。
我們在4Kb的內嵌式動態隨機存取記憶體晶片中實現此提案，於台積65奈米標準CMOS製程下製造。量測結果顯示對於資料保存功率損耗在低壓部分，於室溫下的環境下可以節省高達百分之五十七的功率損耗。

Embedded DRAMs are widely used in many electronic products due to its more cost-effective than SRAM and its faster read/write random access than FLASH. However, increasingly large power consumption is a big problem in SOC system. For this reason, low power design issue should be taken into consideration. For embedded DRAM, the stored data should be confirmed to retain in cell array with conventional period in self-refresh mode. But operating at low voltage, the cell data retention time will eliminate much shorter than that in higher voltage condition. Hence, there is quick refresh and generates an additional AC component of data retention power at low voltage with conventional period.
To solve this problem, we propose a low voltage sensing and write-back control scheme to extend data retention time in lower voltage condition. By operating in write-back phase, it increase potential of data so that margin enhancement in sensing phase achieves to read out data correctly in low voltage mode, and reduces power consumption in self-refresh mode.
A low voltage sensing and write-back scheme is implemented in a 4Kb embedded DRAM macro, which is fabricated in TSMC 65nm Generic CMOS process. The measurement results show that, 57% reduction of data retention power in low voltage can achieve at room temperature.

Contents
Contents v
List of Figures vii
List of Tables ix
Chapter 1 1
1.1 Low Power Embedded-DRAM Applications 1
1.2 Challenges of Low Power Embedded DRAM 2
1.3 Overview of This Thesis 4
Chapter 2 5
2.1 Embedded DRAM Description 5
2.2 Structure of Embedded DRAM 6
2.3 Write Operation 7
2.4 Read Operation 8
2.5 Refresh Operation 9
Chapter 3 11
3.1 Cell Structure 11
3.1.1 Capacitor Structure 13
3.1.2 Gain Cell 14
3.2 Data Retention Time 15
3.3 Leakage Mechanisms 16
3.3.1 Sub-threshold Current (I1) 17
3.3.2 Gate-Induced Drain Leakage (I2) 18
3.3.3 Gate-Oxide Tunneling Current (I3) 20
3.3.4 Hot carrier injection Current (I4) 21
3.3.5 Reverse-Biased Junction BTBT Current (I5) 23
3.3.6 Punch-Through Current (I6) 24
3.4 Power Consumption 24
3.5 Previous Works 26
3.5.1 Conventional Latch-Type voltage Sense Amplifier 26
3.5.2 Published Sensing Schemes 28
Chapter 4 31
4.1 Design Challenge 31
4.1.1 Threshold Voltage in Process 32
4.2 Motivation of Proposed Sensing Control Scheme 33
4.3 Proposed Sensing Control Scheme 34
4.3.1 Structure of Proposed Sense Amplifier 34
4.3.2 Sensing Operations 36
4.4 Analyses of Proposed Sensing Control Scheme 40
4.4.1 Power Reduction in Write / Read Mode 40
4.4.2 Refresh Period 42
4.4.3 Capacitor Analysis of Proposed Sensing Scheme 44
Chapter 5 46
5.1 Macro of Embedded DRAM 46
5.1.1 Memory Cell Arrays 47
5.1.2 Peripheral Circuits 48
5.2 Design for Test Chip 49
Chapter 6 50
6.1 Measurement Results 50
6.2 Conclusions and Future Work 54

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