近年來，由於製程上的限制導致IC越來越難隨著Moore’s law的曲線所成長。為了保持在Moore’s law的曲線上，Through-silicon via (TSV)架構的3D IC是一種廣為接受的作法。由於在3D IC中，垂直的連接距離相較於其他堆疊技術更加縮短，其性能也可因此提升。為了實現3D堆疊的架構，目前有三種方法: wafer-to-wafer (W2W), die-to-wafer (D2W), 以及die-to-die (D2D)。在本研究中，我們假設使用D2W的方式。此外，在半導體中記憶體是最重要的產品；而且，由於資料通訊以及智慧手持裝置的快速發展及增長，對於記憶體的需求也越來越大。近年來，為了達到更高的頻寬與容量，利用TSV作為垂直通訊方式的三維動態隨機存取記憶體 (3D DRAM)被認為是一種可行的方式。然而，為了實現3D DRAM所額外加入的製程中卻可能導入新的defects。每項額外的製程都可能導入相關的defects並降低整體良率。為了預防良率急遽下降，在TSV相關製程的前後可能需要針對3D DRAM進行測試。本研究專注於3D IC生產、測試與封裝流程中的TSV生產製程。我們利用空間與時間的分析去分析來自ATE的測試資料。我們將TSV陣列分成數個區域，並比較不同區域之間的良率，試圖找出misalignment偏移的趨勢。此外，我們將有缺陷的TSV與周圍同樣有缺陷的TSV合併為群組，並嘗試將TSV陣列中的TSV分成不同的群組。本研究在的綜合偵測準確率可達到92.392%，對於random failure的準確率可達到99.9843%，對於cluster failure的準確率可達到97.2268%，而對於misalignment的準確率可達到79.8066%

Recently, keeping Moore’s law is more difficult because of the limitations of the process. Through-silicon via (TSV) based three dimensional integrated circuit (3D IC) is a popular way to meet the law. Thanks to the shorter vertical interconnection paths in 3D IC, its performance can be better than other packages or stacking technologies. There are many methods to stack dies together, e.g., wafer-to-wafer (W2W), die-to-wafer (D2W), and die-to-die stacking (D2D). In this work, without loss of generality, we assume the D2W stacking process is adopted. Moreover, memory is the most important product in semiconductors, and thanks to the rapid growth of data communication and smart handheld devices, the requirement of semiconductor memory is also growing. Recently, three dimensional DRAM (such as Wide-IO, Wide-IO2, HBM, etc.) which utilizes TSVs as the vertical paths to communicate between dies is considered as a good approach to achieving higher bandwidth and larger capacity. However, new defects can be introduced during the extra steps in manufacturing the 3D DRAM. Each added step may introduce its own type of new defects, reducing the overall yield. To prevent dramatic yield loss, the 3D DRAM may need to be tested before and/or after TSV fabrication. This work focuses on the TSV fabrication process, which is part of the entire wafer fabrication, packaging and testing flow for 3D-IC products. We analyze the test data from automatic test equipment (ATE) by spatial and temporal analysis. We separate the TSV array into several regions, and try to find the trend of misalignment by comparing the yields of these regions. In addition, we group failed TSVs which are close to each other. This work can get 92.392% in total detection accuracy, and 99.9843% for random failure, 97.2268% for cluster failure, and 79.8066% for misalignment.

Abstract i
Contents ii
List of Figures iv
List of Tables viii
Chapter 1 Introduction 1
1.1 3D IC 1
1.2 3D DRAM 1
1.3 Abnormality Detection for TSV Process 2
1.4 Organization of the Thesis 3
Chapter 2 Background 4
2.1 3D IC Stacking Process 4
2.2 Specific Defects in TSV-Based 3D IC 6
2.3 Test Flow for 3D Stacked Chips 7
2.4 Abnormality in the Stacking Process 10
Chapter 3 Abnormality Detection for TSV Process 11
3.1 Overview 11
3.2 Data Parse and Rebuild 13
3.2.1 SPEC Files 13
3.2.2 Test Data 16
3.3 Misalignment Detection 16
3.4 Cluster Failure & Random Failure Detection 19
3.5 Temporal and Spatial Variance Analysis (TSVA) 22
3.5.1 Misalignment: 22
3.5.2 Cluster Failure: 23
3.5.3 Random Failure: 23
Chapter 4 Test Bench Generator 25
4.1 SPEC Files 26
4.2 Cluster and Random Failure 28
4.3 Misalignment 30
Chapter 5 Experimental Results 35
5.1 Single Failure 35
5.1.1 Misalignment 35
5.1.2 Cluster Failure 40
5.2 Multiple Failures 42
5.2.1 Misalignment and Cluster Failure 42
5.2.2 Cluster Failure and Random Failure 44
5.2.3 Misalignment, Cluster Failure, and Random Failure 48
5.3 Uncut Wafer Bin Map Rebuild and Analysis 52
5.3.1 Uncut Wafer Bin Map Rebuild 53
5.3.2 Temporal and Spatial Variance Analysis 54
Chapter 6 Conclusions and Future Work 56
Bibliography 57

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