隨著科技的進步，奈奎斯特類比數位轉換器不斷在操作速度與解析度上做改進，從快閃式類比數位轉換器、兩階段式類比數位轉換器、管線式類比數位轉換器至連續漸進式類比數位轉換器，其最終目標皆是在速度與解析度上找到一個完美的平衡。因此本論文題出了兩種高速類比數位轉換器的架構。

首先為一個時域分析模式下的連續漸進式類比數位轉換器，藉由線性的壓控時脈延遲與時間數位轉換器，在一開始的前七個位元取代了以往使用的電壓比較器，透過將各種輸入壓差的延遲時間差線性化後，再由時間數位轉換器找出輸入差值範圍，最後再回到連續漸進式類比數位轉換器輔以電壓比較器做最後五個位元的逼近，不僅大幅節省了連續漸進式類比數位轉換器其電荷重新分佈之次數，更提高傳統連續漸進式類比數位轉換器的操作速度並降低其耗能，並且為了降低因電容之間的匹配程度所產生的誤差，在最後的五個位元中加入了帶餘位元的機制，可在允許範圍內有效修正比較器因電容之間的不匹配所產生錯誤的判斷，提升類比數位轉換器的精準度。

最後則提出一前瞻的高速電流模式之導管式類比數位轉換器，其跳脫過去導管式類比數位轉換器常用的交換電容技巧，藉由電流鏡取代運算放大器的角色，使其不再受限於運算放大器的增益與操作頻率，大幅提升操作速度，並寄望未來能結合分時多工的技術，希望能在65奈米製程下達到4GHZ取樣速率、10位元解析精準度的目標。

As technology improve rapidly, the operation rate and resolution of Nyquist Analog to Digital Converter (ADC) are getting faster and higher. Such as Flash ADC、Two-stage ADC、Pipelined ADC and Successive Approximation Register ADC. There is only one goal, to make the operation rate and resolution matched perfectly. We propose two kinds of ADC’s architecture in this paper.

At first we propose a time analysis SAR ADC, which contain linear voltage control delay line and time to digital converter to replace voltage type comparator, get 7-bit resolution. The linear voltage control delay line take input signal difference as it’s input and generate delay time according to the amount of input signal difference linearly. After we get the delay time, time to digital converter can resolve it to digital thermal code. Thermal code go through an encoder change into binary code and send to control logic to make capacitor array subtract corresponding input signal difference, make input signal approach to each other rapidly. Which greatly reduce the operation time and the times of charge redistribution, save many power consumption. In order to improve the effect of capacitor mismatch, we add some redundant in the last 5-bit to calibration errors which cause by capacitor mismatch.

At last we propose a high speed current mode pipelined ADC, it’s unlike traditional architecture which often use switch capacitor to provide signal gain. We use current mirror to replace operational amplifier, which increase to operation speed and reduce gain error. In the future, this current ADC may combine with time interleaved technology accomplish a 4GS/s 10-bit ADC in tsmc 65nm process.

目錄
中文摘要……………………………………………………………………………9
英文摘要……………………………………………………………………………10
前言…………………………………………………………………………………11
第一章 簡介………………………………………………………………………..12
1.1類比數位轉換器種類介紹……………………………………………………..12
1.1.1快閃式類比數位轉換器……………………………………………………...12
1.1.2連續漸進式類比數位轉換器………………………………………………...13
1.1.3導管式類比數位轉換器……………………………………………………...14
1.2類比數位轉換器相關參數介紹……………………………………………….15
1.2.1奈奎斯特取樣定理………………………………………..………………….15
1.2.2量化物差………………………..…………………………………………….15
1.2.3最小意義單元………………………………………………………………...17
1.2.4微分非線性…………………………………………………………………...17
1.2.5積分非線性…………………………………………………………………...18
1.2.6增益偏差……………………………………………………………………...18
1.2.7直流偏差……………………………………………………………………...18
1.2.8信號與雜訊失真比…………………………………………………………...19
1.2.9有效位元數…………………………………………………………………...19
第二章 操作原理與子電路設計…………………………………………………..20
2.1連續漸進式類比數位轉換器操作原理………………………………………..20
2.2連續漸進式類比數位轉換器子電路設計……………………………………..22
2.2.1追蹤保持電路………………………………………………………………...22
2.2.2靴帶電路……………………………………………………………………...22
2.2.3比較器………………………………………………………………………...23
2.2.4時脈產生器…………………………………………………………………..25
2.2.5連續漸進式邏輯……………………………………………………………..25
2.2.6二位元電容陣列數位類比轉換器…………………………………………..26
2.3導管式類比數位轉換器操作原理………………………………………….....27
2.4導管式類比數位轉換器子電路設計……………………………………….....29
2.4.1取樣保持電路………………………………………………………………..29
2.4.2子類比數位轉換器…………………………………………………………..29
2.4.3倍乘式數位類比轉換器……………………………………………………..30
2.4.4數位編碼器…………………………………………………………………..30
第三章 時域分析之連續漸進式類比數位轉換器…………………………….....34
3.1連續漸進式類比數位轉換器架構選擇…………………………………….....34
3.2時域分析之連續漸進式類比數位轉換器之運作模式…………………….....36
3.3電路架構之設計與實現…………………………………………..……….…..37
3.3.1靴帶電路……………………………………………………………….….....37
3.3.2線性壓控時脈延遲子電路…………………………………………………..38
3.3.3時間數位轉換器……………………………………………………………..42
3.3.5 5位元帶冗餘位元之連續漸近式類比數位轉換器………………………...43
3.3.6比較器………………………………………………………………………..46
3.3.7電路模擬結果……………………………………………………………......47
第四章1GS/s 6-Bit電流模式之導管式類比數位轉換器……………………….49
4.1導管式類比數位轉換器之架構選擇……………………………………….....49
4.2兩階段類比數位轉換器之運作模式………………………………………….50
4.3電路架構之設計與實現…………………………………………………….....50
4.3.1整體電路架構………………………………………………………………..50
4.3.2轉導電路……………………………………………………………………..52
4.3.3取樣及電流放大器…………………………………………………………..53
4.3.4 1.5位元子類比數位轉換器………………………………………………....55
4.3.5 2位元子類比數位轉換器…………………………………………………...56
4.3.6全差動比較器………………………………………………………………..57
4.3.6數位編碼器…………………………………………………………………..58
4.3.7模擬結果……………………………………………………………………..59
第五章 總結……………………………………………………………….………61
參考文獻……………………………………………………………….…………..63

圖目錄
類比數位轉換器效能比較圖………………………………………………………11
圖1.1快閃式類比數位轉換器…………………………………………………….12
圖1.2連續漸進式類比數位轉換器……………………………………………….13
圖1.3導管式類比數位轉換器…………………………………………………….14
圖1.4倍乘式數位類比轉換器…………………………………………………….14
圖1.5奈奎斯特取樣定理………………………………………………………….15
圖1.6量化誤差…………………………………………………………………….16
圖1.7量化雜訊的機率密度函數……………………………………..…………...17
圖1.8 DNL示意圖……………………………………..…………………...……...17
圖1.9 增益偏差示意圖……………………………………..……………...……...18
圖1.10直流偏差示意圖……………………………………..……………...……..19
圖2.1單端連續漸進式類比數位轉換器操作示意圖…………………………….20
圖2.2雙端連續漸進式類比數位轉換器操作示意圖…………………………….21
圖2.3雙端連續漸進式類比數位轉換器電容陣列切換示意圖………………….21
圖2.4追蹤保持電路與其行為示意圖…………………………………………….22
圖2.5靴帶電路架構圖…………………………………………………………….23
圖2.6靜態、動態比較器電路架構圖…………………………………………….24
圖2.7軌對軌比較器電路架構圖………………………………………………….24
圖2.8時脈產生器………………………………………………………………….25
圖2.9同步連續漸進式邏輯……………………………………………………….26
圖2.10非同步連續漸進式邏輯…………………………………………………...26
圖2.11二位元電容陣列之數位類比轉換器……………………………………...27
圖2.12導管式類比數位轉換器時脈分佈………………………………………...28
圖2.13(a) 1.5位元階段子電路輸入-輸出位階轉換線………………………...28
圖2.13(a) 1.5位元階段子電路輸入-輸出殘值轉換線………………………...28
圖2.14取樣保持電路……………………………………………………………...29
圖2.15倍乘式數位類比轉換器…………………………………………………...30
圖2.15正確的判斷準位…………………………………………………………...31
圖2.16首級產生錯誤的判斷準…………………………………………………...32
圖2.17 4位元1.5位元/階數位錯誤更正操作範例………………………………33
圖3.1壓控時脈延遲子電路與時脈……………………………………………….34
圖3.2帶冗餘位元修正模式……………………………………………………….35
圖3.3時域分析之連續漸進式類比數位轉換器操作流程圖…………………….36
圖3.4時域分析之連續漸進式類比數位轉換器………………………………….37
圖3.5靴帶電路架構圖…………………………………………………………….38
圖3.6靴帶電路模擬結果………………………………………………………….38
圖3.7 線性壓控時脈延遲子電路…………………………………………………39
圖3.8 |輸入訊號差|與控制訊號關係圖…………………………………………41
圖3.9 |V_ip-V_in |與∆t關係圖………………………………………………..……41
圖3.10時間數位轉換器…………………………………………………………...42
圖3.11時間數位轉換器操作示意圖……………………………………………...43
圖3.12 5位元帶冗餘位元之電容陣列……………………………………………43
圖3.13電容不匹配分佈情形……………………………………………………...44
圖3.14電容切換穩定時間示意圖………………………………………………...45
圖3.15帶冗餘位元制定流程……………………………………………………...45
圖3.16靜態比較器架構圖………………………………………………………...46
圖3.17比較器模擬結果…………………………………………………………...47
圖3.18整體ADC規格設計……………………………………………………….47
圖3.19 Pre-simulation模擬結果…………………………………………………...48
圖4.1簡易放大器架構……………………………………………………………..49
圖4.2非理想效應化簡……………………………………………………………..50
圖4.3兩階段類比數位轉換器…………………………….……………………….50
圖4.4電流切換導管式類比數位轉換器………………..………………………....52
圖4.5轉導電路………………………………………….………………………….52
圖4.6取樣及電流放大器……………………………………..……………………53
圖4.7電流切換器………………………………………………………………......54
圖4.8 1.5位元子類比數位轉換器………………………...……………………….55
圖4.9 1.5位元子類比數位轉換器模擬結果………………………………………56
圖4.10 2位元子類比數位轉換器………………………………………………….56
圖4.11 2位元子類比數位轉換器模擬結果……………………………………….57
圖4.12全差動比較器………………………………………………………………58
圖4.13數位編碼器…………………………………………………………………58
圖4.14 TSPC………………………………………………………………………...59
圖4.14 Pre-simulation模擬結果………………………………………………........60
圖5.1第五代通訊系統目標架構圖…………………..……………………….........61

表目錄
表3.1 |V_ip-V_in |與∆t對應表………………………………………………….....44
表4.1類比數位轉換器規格表…………………………………………………....60

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