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作者(中文):劉冠麟
作者(外文):Liu, Kuan Lin
論文名稱(中文):應用於多光譜遙測衛星之時間延遲多次積分線性掃描互補式金氧半導體影像感測器
論文名稱(外文):A Time Delay Multiple Integration Linear CMOS Image Sensor for Multispectral Satellite Telemetry
指導教授(中文):謝志成
指導教授(外文):Hsieh, Chih Cheng
口試委員(中文):鄭國興
邱進峯
鄭桂忠
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程學系
學號:102061582
出版年(民國):106
畢業學年度:105
語文別:英文
論文頁數:83
中文關鍵詞:時間延遲積分互補式金氧半導體影像感測器
外文關鍵詞:Time Delay IntegrationCMOS Image Sensor
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本論文提出一個應用於多光譜(Multispectral)衛星遙測之線性互補式金氧半導體影像感測器,利用時間延遲多次積分(Time Delay Multiple Integration)技術提高影像的訊雜比(Signal-to-Noise Ratio)。
為了得到高電荷轉電壓增益,本論文採用Y型轉Δ型(Y-to-Delta)金屬-氧化物-金屬(Metal-Oxide-Metal)電容結構為積分電容之電容反饋跨阻抗放大器(Capacitive Trans-impedance Amplifier)作為像素架構。利用本論文所提出之類比與數位累積的混合架構,所實作之時間延遲多次積分器配合加法器與靜態隨機存取記憶體(Static Random-Access Memory)庫,將時間延遲積分(Time Delay Integration)、多次取樣(Multiple Sampling)、以及類比數位轉換等功能整合在單一晶片上。利用兩組記憶體庫,數位式相關雙採樣(Digital Correlated Double Sampling)也完成實現在此實作中。
為了驗證本電路,一個8級、128行的時間延遲積分線性互補式金氧半導體影像感測器原型使用0.18微米1P6M標準互補式金氧半導體製程製作,晶片總面積為2500×5200 μm2。在8級時間延遲積分、以及每次時間延遲積分中多次取樣64次的操作下,量測結果顯示在線時間為414.72微秒的操作時間下,感光靈敏度為40.42 V/lux∙s,訊雜比提升約為9.37dB,在1.8伏特的操作電壓下,系統功耗為17.77毫瓦。
This thesis presents a linear CMOS image sensor for multispectral (XS) satellite telemetry with time delay multiple integration (TDMI) technique to improve the signal-to-noise ratio (SNR) of imaging.
To achieve high conversion gain, the capacitive trans-impedance amplifier (CTIA) based pixel with Y-to-Delta (Y-Δ) metal-oxide-metal (MOM) capacitor network as the integration capacitor is adopted in this work. With the proposed hybrid structure of analog and digital accumulation, the implemented time delay multiple integrator, cooperating with the adder and static random-access memory (SRAM) bank, integrates the functions of time delay integration (TDI), multiple sampling (MS), and analog-to-digital conversion in a single chip. By using two memory bank, the digital correlated double sampling (D-CDS) has also been implemented in this work.
An 8-stage 128-column TDMI linear CMOS image sensor prototype was fabricated in 0.18-μm 1P6M standard CMOS technology with a chip area of 2500×5200 μm2. With an operation of 8 stages TDI and 64 times MS per TDI stage, the measurement result shows that the sensitivity is 40.42 V/lux∙s at a line time of 414.72 μs, the resulting SNR improvement is 9.37 dB, and operating at 1.8 V supply voltage, the power consumption is 17.77 mW.
Abstract . ii
Content . iii
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Contribution 3
1.3 Thesis Organization 5
Chapter 2 Background Information 6
2.1 Fundamentals of CMOS Image Sensor 6
2.1.1 Active Pixel Sensor (APS) 7
2.1.2 Fundamental Terms of Image Sensor 12
2.1.3 Noise in Image Sensor 14
2.1.4 Correlated Double Sampling (CDS) 16
2.2 Satellite Background 17
2.2.1 Satellite Motion 17
2.2.2 Line-Scan Image Sensor 18
2.2.3 Panchromatic sensor and Multispectral sensor 19
2.3 Time Delay Integration (TDI) Technique 21
2.3.1 The Operation of TDI 21
2.3.2 The Principle of TDI 22
2.3.3 Review of the State-of-the-Art TDI Structure 23
2.4 Design Consideration of Multispectral Sensor 25
2.4.1 Physical Specification of Detector in Outer Space 25
2.4.2 Limitation of Large Pixel Pitch 26
2.4.3 Dominated Noise in Multispectral Sensor 28
2.5 Summary 31
Chapter 3 High CG CTIA Pixel, Proposed Time Delay Multiple Integration, and D-CDS 33
3.1 High CG Capacitive Trans-Impedance Amplifier Based Pixel 33
3.1.1 Review on Capacitive Trans-Impedance Amplifier 33
3.1.2 Principle of Y-to-Delta (Y-Δ) network 34
3.1.3 Noise of CTIA Based Pixel 36
3.2 Time Delay Multiple Integration Technique 37
3.2.1 Multiple Sampling in TDI 37
3.2.2 First-Order Incremental Sigma Delta Modulator (I-SDM) 38
3.2.3 Proposed Time Delay Multiple Integration (TDMI) Technology 40
3.3 Digital Correlated Double Sampling 47
3.4 Summary 49
Chapter 4 Prototype Implementation of Time Delay Multiple Integration Linear Image Sensor for Multispectral Satellite Telemetry 50
4.1 System Architecture of Proposed Linear Sensor 50
4.2 CTIA Based Pixel with Y-to-Delta (Y-Δ) network 52
4.3 Column-wise Time Delay Multiple Integration 56
4.3.1 Circuit Implementation of TDMI 56
4.3.2 Switch Capacitor Operation in TDMI 57
4.3.3 OPAMP, Comparator, and Counter in TDMI 58
4.3.4 Simulation Result of TDMI 60
4.4 Digital Summing Circuits Implementation 61
4.4.1 Ripple-Carry Adder 61
4.4.2 Read/Write Latch 62
4.4.3 SRAM Bank 63
4.4.4 Digital Summing Circuit Operation 64
4.5 Chip Operation 65
4.6 Summary 66
Chapter 5 Measurement Results 67
5.1 Chip Implementation 67
5.2 Measurement Environment Setup 69
5.3 Sensor Measurement 71
5.3.1 High & Low Conversion Gain 71
5.3.2 TDMI Measurement 71
5.3.3 Line-Scan Imaging 74
5.3.4 Result Discussion 75
5.4 Performance Summary and Comparison 78
Chapter 6 Conclusion 79
6.1 Summary 79
6.2 Future Work 80
Bibliography 81
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