在大多數的電子系統中，半導體記憶體被視為是不可或缺的元件。因此如何增加半導體記憶體的良率和可靠度變得越來越重要。在先進製程技術下，單一積體電路中越來越多的缺陷是尚未被模型化，而且無法在主要輸出埠以傳統的邏輯電平錯誤或電壓量測進行測試。而時間延遲測試和電流量測是兩個重要的方法可以偵測到上述在傳統測試中可能無法被偵測到的缺陷。其中時間延遲測試相對於電流量測方法的發展較為成熟，但是對於大容量記憶體而言，要完整地偵測出全部有可能造成時間延遲的潛藏缺陷是非常耗時而不切實際的作法，所以我們使用電流偵測電路以解決這個問題。
記憶體內建自我測試電路對於測試內嵌式記憶體是一個常用且成熟發展的電路，特別是針對測試靜態功能性錯誤，然而對於時間延遲相關的動態缺陷則需要配合使用複雜的測試演算法和時脈控制。前述測試方法即使可以執行，對於大容量內嵌式記憶體而言，過程依然會非常耗時而不切實際。因此我們嘗試將電流感測電路與既有的內建自我測試電路結合以解決此問題。我們使用的電流感測電路其模型及佈局檔皆是由國立東華大學電機系何盈杰助理教授所研發及提供。在這些基礎上，我們提出「以整合漏電流感測器之記憶體內建自我測試電路降低產品不良率」，而其中作為基底的記憶體內建自我測試電路則是由我們使用BRAINS所產生。整合漏電流感測器之記憶體內建自我測試電路主要運作方式為漏電流感測器將待測電路的漏電流複製然後將其感測結果量化成一個數位的形式，進而其結果可以被內建自我測試電路衡量及分析。
我們使用65奈米互補式金屬氧化物半導體製程技術去實現此記憶體內建自我測試電路，另外使用靜態隨機存取記憶體產生器產生一個容量為8千位元組（2048x32位元）且單通道的記憶體。我們將記憶體內建自我測試電路、靜態隨機存取記憶體及漏電流感測器合併在單一測試晶片作為實驗，並且我們將此設計完成至實體層級。根據詳細的佈局後模擬，整合漏電流感測器之記憶體內建自我測試電路的運作情形符合我們的期待。然而因為對於靜態隨機記憶體而言，漏電流感測器提供額外的負載導致測量到的漏電流數值比我們的預期值低。在進行大量產品的測試之前，這個因素可以藉由漏電流感測器的校準模式來排除。在內建自我測試電路執行測試的初始，我們可以透過漏電流感測器的校準模式將參考電流儲存至內建自我測試電路內，並且內建自我測試電路以此為基準和測量後所得到的電流值來判斷待測電路的正確與否。我們所提出的整合漏電流感測器之記憶體內建自我測試電路可以進行原先的功能性測試，並且可以更進一步地測量靜態隨機記憶體的漏電流。我們所提出的設計可以感測到最小為30微安培的電流，而此電路的面積則為905x905平方微米。

Semiconductor memory is considered an essential component in almost all electronic systems. Increasing the yield and reliability of semiconductor memory becomes a more and more important issue. It is well known that in advanced process technologies, more and more defects in an IC cannot be modeled and tested by conventional logic-level faults or voltage measurements at the primary outputs. Delay (timing) testing and current measurement, e.g., are two important approaches, which help cover such defects that may otherwise escape conventional tests. Delay or at-speed test is relatively mature, but a complete test that covers all potential timing defects can be slow and impractical for large memories, so we address the issue using a current measurement circuit (current sensor).
Memory built-in self-test (BIST) is popular and mature for embedded memories, especially for static functional faults. For timing related dynamic defects, however, complicated test algorithms and clock schemes may be required. Even if they can be executed at-speed, the process still can be too slow and impractical for large embedded memories. We try to address the issue by integrating a current sensor with the existing BIST design. We reuse the current sensor circuit developed by Prof. Ying-Chieh Ho of NDHU, who provides the current sensor circuit and layout. Based on that, we propose a leakage-current sensor enhanced memory BIST for reducing defect level of embedded RAM, where the original memory BIST was generated by BRAINS (BIST for RAM in seconds). The leakage-current sensor mirrors the leakage-current from the circuit under test, and then quantizes the result into a digital form that is to be evaluated by the BIST circuit.
We use a commercial 65nm CMOS technology (with standard cell library) to implement the memory BIST design, and use a commercial SRAM compiler to generate an 8KB (2048x32 bits) single-port SRAM. As an experiment, we integrate the memory BIST, SRAM, and the leakage-current sensor into a single test chip, and finish the design at the physical level. Based on detailed post-layout simulation, we conclude that the leakage-current sensor enhanced memory BIST works as we expected. However, the extra loading of the current sensor to the SRAM results in a lower measurement current than expected, but this factor can be taken care of in the calibration process (to determine the reference current) before mass production test. The reference current will then be entered into the BIST module in the beginning of the test session for go/no-go comparison with the measured current. In summary, the proposed leakage-current sensor enhanced memory BIST can do the original functional test, and furthermore it can sense the leakage-current of the SRAM. The minimum value of the current detected by our design is 30 uA. The total area of our design is 905x905 um2.

Abstract i
Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Memory Test 1
1.2 Fault Models and March Algorithms 4
1.3 Leakage-Current in Memory 4
1.4 Proposed Approach 5
1.5 Thesis Organization 6
Chapter 2 Traditional Memory BIST and Leakage-Current Sensor 7
2.1 Template of Memory BIST 7
2.2 Memory BIST Architecture 9
2.2.1 Controller 10
2.2.2 Sequencer 12
2.2.3 Test Pattern Generator 13
2.3 Leakage-Current Sensor 15
2.4 SRAM Compiler and Specification 19
Chapter 3 Leakage-Current Sensor Enhanced Memory BIST 21
3.1 Configuration 22
3.1.1 Combinations of BG 22
3.1.2 Combinations of Command 23
3.1.3 Built-in March Algorithm 25
3.2 Modified Sequencer 25
3.3 Modified Diagnostic Syndrome 26
3.4 FSM of Leakage-Current Sensor 27
Chapter 4 Chip Implementation 28
4.1 Floorplan 28
4.2 Power Domain 30
4.3 Chip Layout 32
Chapter 5 Experimental Results 33
5.1 Experiment Setup 33
5.2 Simulation Results 33
5.2.1 Diagnosis Mode 34
5.2.2 Fout Curve 37
5.2.3 Sensing Functions 37
Chapter 6 Conclusions and Future Work 41
6.1 Conclusions 41
6.2 Future Work 41
Bibliography 42

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