傳統物件辨識的比對方法，需透過建構許多特徵點來進行兩張物件的比對，這些特徵點需要能夠應對物件的放大、縮小及旋轉，而不同的特徵點間也需要具有一定的差異來確保特徵點的獨特性。由於特徵點需要滿足上述的要求，建構一個物件的特徵點所花費的計算時間相對的就被拉長，以Intel Core i5 4440 + Matlab實作，平均一個物件所需要的時間為2.7(s)，如果要應用在即時的系統上面，仍有一段很大的差距。
在眾多的物件比對演算法中，SIFT演算法是較受歡迎的演算法之一，由SIFT演算法所建構出來的描述子能夠應對各種不同的情況。特徵點的建構主要分成三個部分，分別為feature location、feature extraction跟descriptor generation，在SIFT演算法中花費最長的部分在feature location及descriptor generation，分別占用的約30%及60%的計算時間，所以想辦法減少這兩個步驟所需的時間就可以將演算法應用在即時的系統上面。
由於原本的SIFT演算法所建構的描述子需要花費太大的運算資源及太長的運算時間，我們提出一個二位元的描述子來取代原本的描述子，二位元描述子能夠有效降低運算的複雜度以及記憶體的使用，並且應用在小角度的物件偏移比對上面也能有很好的表現，在運算的時間上面，以相同的系統Intel Core i5 4440 + Matlab去做模擬所需的時間約為0.57(s)，跟傳統SIFT演算法相比只需要約20%的計算時間。
我們更進一步提出硬體的架構來加速改進後的演算法，採用TSMC90nm的製程來實作，工作頻率可達100MHz，在HD1080p的物件大小下能達到30 frames/s，因此也可以應用在即時的系統上。

Scale-Invariant Feature Transform (SIFT)[1][2] has lately attracted attention in computer vision as a robust feature point detection algorithm which is invariant for scale, rotation and illumination change. However, its computational complexity is too high to apply on practical real-time applications. The iterated Gaussian blurred operations on images lead to long computational latency and high memory requirement. In addition, the gradient histogram based descriptor needs lots of calculation and costs about 60% of total calculation time on generating the descriptor.
We propose a binary-based descriptor that uses the intensity difference between neighboring pixels. The binary descriptor has the advantage of lower computational complexity and memory usage. For the use of the classifying the object, the binary descriptor also have the acceptable accuracy compared with the traditional histogram based descriptor. The proposed binary descriptor has 7.07x speed up than the original SIFT descriptor. In addition, it has 4.73x speed up compared with original SIFT algorithm[2].
The hardware implementation of the SIFT algorithm with the proposed binary descriptor applies parallel computing on the stage of feature location to accelerate the computing time on detecting feature points. The final implementation uses about 493-K gate count with 90-nm CMOS technology, and offers 7600 feature points/frame for 1080p images at 30 frames/s at the clock rate of 100 MHz.

Chapter 1 Introduction 1
Chapter 2 Related Work 4
Chapter 3 Background 7
3.1 Scale-Invariance Feature Transform 7
3.2 Layer parallel Scale-Invariance Feature Transform 17
Chapter 4 Binary Descriptor and Matching 21
4.1 Algorithm and Parameter Selected 21
4.2 Binary Descriptor 25
4.3 Image Matching 28
Chapter 5 Performance Evaluation 30
5.1 Environment Setting 30
5.2 Simulation Result 31
Chapter 6 Hardware Implementation 35
6.1 Hardware Implementation 35
6.2 Result of Hardware Implementation 47
Chapter 7 Conclusions and Future Work 51
7.1 Conclusions 51
7.2 Future Work 52

Bibliography 52

[1]. Lowe, David G. "Object recognition from local scale-invariant features."Computer vision, 1999. The proceedings of the seventh IEEE international conference on. Vol. 2. Ieee, 1999.
[2]. Lowe, David G. "Distinctive image features from scale-invariant keypoints."International journal of computer vision 60.2 (2004): 91-110.
[3]. Zhang, Qi, et al. "SIFT implementation and optimization for multi-core systems." Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on. IEEE, 2008.
[4]. Hsu, Gee-Sem, Chyi-Yeu Lin, and Jia-Shan Wu. "Real-time 3-D object recognition using Scale Invariant Feature Transform and stereo vision."Autonomous Robots and Agents, 2009. ICARA 2009. 4th International Conference on. IEEE, 2009.
[5]. Lalonde, Marc, et al. "Real-time eye blink detection with GPU-based SIFT tracking." Computer and Robot Vision, 2007. CRV'07. Fourth Canadian Conference on. IEEE, 2007.
[6]. Bonato, Vanderlei, Eduardo Marques, and George Constantinides. "A parallel hardware architecture for scale and rotation invariant feature detection."Circuits and Systems for Video Technology, IEEE Transactions on 18.12 (2008): 1703-1712.
[7]. Yao, Lifan, et al. "An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher." Field-Programmable Technology, 2009. FPT 2009. International Conference on. IEEE, 2009.
[8]. Huang, Feng-Cheng, et al. "High-performance SIFT hardware accelerator for real-time image feature extraction." Circuits and Systems for Video Technology, IEEE Transactions on 22.3 (2012): 340-351.
[9]. Bay, Herbert, Tinne Tuytelaars, and Luc Van Gool. "Surf: Speeded up robust features." Computer vision–ECCV 2006. Springer Berlin Heidelberg, 2006. 404-417.
[10]. Grabner, Michael, Helmut Grabner, and Horst Bischof. "Fast approximated SIFT." Computer Vision–ACCV 2006. Springer Berlin Heidelberg, 2006. 918-927.
[11]. Derpanis, Konstantinos G., Erich TH Leung, and Mikhail Sizintsev. "Fast scale-space feature representations by generalized integral images." Image Processing, 2007. ICIP 2007. IEEE International Conference on. Vol. 4. IEEE, 2007.
[12]. Ke, Yan, and Rahul Sukthankar. "PCA-SIFT: A more distinctive representation for local image descriptors." Computer Vision and Pattern Recognition, 2004. CVPR 2004. Proceedings of the 2004 IEEE Computer Society Conference on. Vol. 2. IEEE, 2004.
[13]. Harris, Chris, and Mike Stephens. "A combined corner and edge detector."Alvey vision conference. Vol. 15. 1988.
[14]. Chiu, Liang-Chi, et al. "Fast SIFT design for real-time visual feature extraction."Image Processing, IEEE Transactions on 22.8 (2013): 3158-3167.
[15]. Andraka, Ray. "A survey of CORDIC algorithms for FPGA based computers."Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays. ACM, 1998.
[16]. Lindeberg, Tony. "Scale-space theory: A basic tool for analyzing structures at different scales." Journal of applied statistics 21.1-2 (1994): 225-270.
[17]. Mikolajczyk, Krystian, and Cordelia Schmid. "Scale & affine invariant interest point detectors." International journal of computer vision 60.1 (2004): 63-86.