近來，大容量資料儲存裝置的廣泛運用造就了反及閘式快閃記憶體無可取代的地位。憑藉著比其他平面半導體記憶體還小的元件面積，反及閘式快閃記憶體掌握了高元件密度以及低製造成本的優勢。
隨著科技的發展，現在最先進的反及閘式快閃記憶體已經微縮到小於二十奈米的等級。然而，製程微縮使得平面半導體的製造越來越困難。最糟的是，因製造困難而上升的成本甚至會比製程微縮所減少的成本還多。為了同時降低成本以及增加記憶體容量，三維反及閘式快閃記憶體應運而生。
由於架構上的限制，反及閘式快閃記憶體的隨機讀取速度十分緩慢。因此，反及閘式快閃記憶體必須以平行讀取來同時輸出大量資料以增加它的市場競爭力。
我們提出一種應用於三維垂直閘極 BE-SONOS 型式反及閘快閃記憶體的逆電流式感測及分層式溫度補償電路。這種逆電流式感測方式可以支援資料平行輸出，並且不受源極線上以及位元線耦合的雜訊影響。此外，此逆電流式感測專用的分層式溫度補償電路可以使之在 -40~125 ̊C下維持一定的資料可靠性。

Nowadays, the wide-spread usage of the large data storage devices contributes to the indispensable status of the NAND Flash memory. With the smallest cell area among the 2D memories, NAND Flash memory holds the superiority in cell density and cost.
The state-of-the-art 2D NAND Flash memory has reached 1X nanometer node. However, the technology scaling makes the fabrication of NAND Flash much more difficult than before. Worst of all, the cost caused by the fabrication difficulty even exceed the cost saved by the shrinking cell size. In order to reduce the bit cost while increasing the storage capacity at the same time, the 3D NAND Flash technology is developed.
Due to the structural limitation, the random access speed of NAND Flash memory is quite slow. As a result, the parallel sensing to simultaneously read out a large amount of data is essential to enhance the competitive capability of it.
We proposed a reverse current sensing scheme for 3DVG BE-SONOS NAND Flash memory with the layer-aware temperature compensation capability. It can support the parallel read to enlarge the data throughput; in addition, the proposed sensing scheme is totally immune to the source line noise and the BL cross-talk noise. Furthermore, the layer-aware temperature compensation can effectively maintain the reliability of the reverse current sensing at -40~125 ̊C.

指導教授推薦書 III
口試委員審定書 IV
摘要 V
ABSTRACT VI
致謝 VII
CONTENTS IX
LIST OF FIGURES XI
LIST OF TABLES XIII
CHAPTER 1. INTRODUCTION 1
1.1 NAND FLASH MEMORY APPLICATION 1
1.2 CHALLENGES OF NAND FLASH MEMORY 4
1.3 OVERVIEW OF THE THESIS 7
CHAPTER 2. THREE-DIMENSION VERTICAL GATE (3DVG) BE-SONOS TFT NAND FLASH MEMORY 8
2.1 BANDGAP ENGINEERED SILICON-OXIDE-NITRIDE- OXIDE-SILICON (BE-SONOS) MEMORY DEVICE 8
2.2 ARRAY ORGANIZATION 10
2.3 READ OPERATION 13
2.4 PROGRAM OPERATION 14
2.4.1 Self-Boost Program Inhibit (SBPI) Technique 14
2.4.2 Program Verification Algorithm 17
2.4.3 Incremental Step Pulse Programming (ISPP) 18
2.5 ERASE OPERATION 20
2.5.1 Hole Tunneling Erase 20
2.5.2 Self-Boost Erase Inhibit Technique (SBEI) 21
2.5.3 Erase Verification 22
CHAPTER 3. PREVIOUS SENSING SCHEME 24
3.1 PAGE BUFFER STRUCTURE 24
3.2 FORWARD VOLTAGE SENSING 26
3.2.1 Basic Concept 26
3.2.2 Interleaving Architecture 27
3.3 FORWARD CURRENT SENSING SCHEME 29
3.3.1 Basic Concept 29
3.3.2 Multi-Sensing Method 31
3.4 REVERSE VOLTAGE SENSING 33
3.4.1 Basic Concept 33
3.4.2 Temperature Compensation 34
3.4.3 Temperature Compensated BL-Clamp Generator 37
CHAPTER 4. CHALLENGES OF 3DVG NAND FLASH 38
4.1 BL COUPLING NOISE 38
4.2 COMMON SOURCE LINE NOISE 42
4.3 BACKGROUND PATTERN DEPENDENCY (BPD) 43
4.4 LAYER BY LAYER VTH REQUIREMENT 44
4.4.1 Basic Concept 44
4.4.2 Layer-Aware Program Verify (LAPV) 46
4.4.3 Layer-Aware Temperature Compensated BL-Clamp Generator Circuit [58] 47
CHAPTER 5. PROPOSED REVERSE CURRENT SENSING WITH LAYER-AWARE TEMPERATURE COMPENSATION SCHEME 48
5.1 PROPOSED REVERSE CURRENT SENSING 49
5.1.1 Basic concept 49
5.1.2 Circuit Designed for Reverse Read Sensing 51
5.2 PROPOSED LAYER-AWARE TEMPERATURE COMPENSATION SCHEME 52
5.2.1 Programming Policy on Tracking Cells 53
5.2.2 Proposed Circuit for Vth Tracking 55
CHAPTER 6. ANALYSIS AND COMPARISONS 58
6.1 MATHEMATICAL ANALYSIS OF REVERSE CURRENT SENSING 58
6.1.1 General Function of Reverse Current Sensing 58
6.1.2 Compensation on Variation Caused by Temperature and Inter-Layer Difference 59
6.2 SIMULATION WAVEFORM 61
6.3 COMPARISON WITH OTHER WORKS 64
6.3.1 Comparison with Other Sensing Schemes 64
6.3.2 Comparison with Other Layer-Aware Temperature Compensation Scheme 68
CHAPTER 7. CHIP IMPLEMENTATION 69
7.1 TEST CHIP STRUCTURE 69
7.2 DATA PATTERN DESIGN 70
7.3 TEST BLOCKS 70
7.4 LAYOUT AND AREA COST 71
CHAPTER 8. EXPERIMENTS AND CONCLUSION 73
8.1 TEST CHIP 73
8.2 MEASURED WAVEFORMS 73
8.3 CONCLUSIONS AND FUTURE WORK 77
REFERENCE 79

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