在本論文中，我們提出了一個數位至時間轉換器系統，藉由兩個鎖相迴路與一個脈衝窗口產生器實現。在整個數位至時間轉換器系統當中，第一級鎖相迴路的輸出訊號頻率為100 MHz，具有75個相位選擇，時域上則有133.33 ps的時間解析度。由於兩級鎖相迴路的串接式架構，使得第二級鎖相迴路的輸出端100 MHz訊號具有5700個相位選擇，時域上則有1.754 ps的時間解析度。此外，藉由最後一級電路的脈衝窗口產生器處理，使得本系統有12.5 MHz的脈衝訊號輸出，而且依然具有1.754 ps的時間解析度，並且被應用於脈衝雷達。此脈衝雷達傳輸的脈衝訊號的週期為80 ns，其脈衝寬度為1.05 ns。載波訊號7.6 GHz位在第二級鎖相迴路中壓控振盪器的輸出端，藉由脈衝訊號的控制來開啟。藉由多級的延遲移位暫存器的處理，使得時脈訊號在高時間解析度上可以有相位移動與相位回轉的能力。然而，在延遲移位暫存器中的第一級D型正反器中，若沒有足夠的保持時間與設定時間，則會有亞穩態的問題發生。而此狀態的發生會導致相位移動的動作失效。因此，我們特別在D型正反器的輸入D端前加入可規劃式延遲電路，調整其延遲大小來避免亞穩態的狀態發生。此電路系統被實現於台積電(TSMC) 0.65 nm 1P9M的CMOS製程，其輸出的脈衝訊號具有15.48-bit (即45600)個相位選擇。

In this thesis, we propose a digital-to-time converter (DTC) system with two phase-locked loops and impulse window generator (IWG). Among the DTC system, the output signal of the first stage PLL is 100MHz with 75 selections of phase, the time resolution is 133.33 ps. Owing to the structure of two stage cascade PLL, the output signal of the second stage PLL is 100MHz with 5700 selections of phase, the time resolution is 1.754 ps. Furthermore, by the last stage IWG processing, the system has the 12.5 MHz impulse signal with 1.754 ps time resolution, applicated to the impulse radar. The impulse radar transmits impulses with period 80 ns and pulse width 1.05 ns. At the VCO output of the second stage of PLL, the carrier wave 7.6 GHz is turned on by the impulse signal control. By multi-stage of delay shift register (DSR), clock signals can be phase shifting and phase rotation in high time resolution. However, the first stage DFF in the delay shift register have metastability issues, if the data input D doesn’t have enough setup time and hold time. This situation give rise to the failure of phase shifting operation. Therefore, we insert the programmable delay line circuit in front of DFF input D, particularly calibrated the time delay prevent form metastability. The system is implemented in TSMC 0.65 nm 1P9M CMOS process, the output of impulse signal have 15.48-bit (45600) selections of phase.

摘要 I
Abstract II
第一章 緒論 1
1.1簡介 1
1.2研究動機 1
1.3章節介紹 2
第二章 鎖相迴路原理 3
2.1 鎖相迴路線性模型 3
2.2 相位頻率檢測器(Phase Frequency Detector, PFD) 6
2.3 電流泵(Charge Pump, CP) 9
2.4 壓控振盪器(Voltage-Controlled Oscillator, VCO) 13
2.5 除頻器(Divider) 16
2.6 迴路濾波器(Loop Filter, LF) 16
2.7 系統分析 19
第三章 電路設計 24
3.1 數位至時間轉換器(Digital-to-Time Converter, DTC) 24
3.2 PLL1電路架構 26
3.3 PLL2電路架構圖 27
3.4 脈衝窗口產生器 29
3.5 DTC電路系統分析 33
3.6 DFF中的亞穩態問題 37
3.7 隨機位置的CP電流脈衝 41
第四章 電路模擬結果 43
4.1 相位檢測器模擬 43
4.2 電流泵靜態模擬 44
4.3除頻器模擬 48
4.4 VCO模擬結果 50
4.5 Rand Cell模擬與晶片量測結果 52
4.6 高階迴路濾波器模擬 55
4.7 可調式延遲電路模擬 57
4.8 DTC系統模擬 59
4.9 DTC系統佈局 63
第五章 結論 64
5.1 結論 64
5.2 未來展望 65
參考文獻 66
附錄 68

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