類比數位轉換器是類比訊號與數位訊號的主要媒介，因此類比數位轉換器的效能大大影響了訊號接收端的品質，然而隨著資料傳遞量以及速度等需求的增長，高取樣速率高解析度的類比數位轉換器對於整體訊號接收端的解析度影響是漸趨重要的。

目前積體化資料皆以數位的形式運算，以類比的型態呈現，因此類比數位轉換器在系統晶片中扮演著一個重要角色。類比訊號由天線接收端進入系統中，由前端之低雜訊放大器先做預先的放大，將放大後的訊號經過降頻後藉由類比數位轉換器轉換至數位訊號，再將此訊號提供後端數位訊號處理做資料的運算，故類比數位轉換器之轉換效率以及效能對於整個訊號路徑俱有非常重要的影響，且類比數位轉換的過程中，常常遇到元件不理想、時脈的抖動與雜訊等問題，因此如何克服這些困難以產生正確的輸出訊號以提供後方數位訊號處理電路進行運算算是類比數位轉換器成功的關鍵。
隨著科技的進步，類比數位轉換器不斷在速度與解析度上做改進，從快閃式類比數位轉換器、管線式類比數位轉換器與連續漸進式類比數位轉換器，如圖二所示，其每種架構之類比數位器皆具有各自的取向，

本論文主要介紹多通道時間交錯式類比數位轉換器的研究，其中包含了多通道所造成的非理想效應分析、多通道時間交錯式取樣開關模擬結果，而後端類比數位轉換器分為連續漸進式類比數位轉換器以及導管式類比數位轉換器兩個部分介紹，連續漸進式類比數位轉換器為10位元每秒取樣100百萬次有效位元為9.92，DNL與INL為完美結果，平均消耗功率為2.42mW，每次轉換所消耗的平均能量為25fJ，導管式類比數位轉換器電路架構主要由快閃式類比數位轉換器以及切換電容式電路為基底的倍乘式數位類比轉換器所組成

Analog-to-digital converter is the major intermedium of analog signals and digital signals, so the efficiency of analog-to-digital converter greatly affect the quality of the signal at the receiving end. However, with the rapid growth of data transfer volume and speed requirements, high sampling rate high-resolution analog digital converter for the impact on the resolution of overall signal receiving end is becoming much more crucial.

In the thesis, the researches of multi-channel time-interleaved analog-to-digital converter are mainly mentioned which includes the non-ideal effects analysis of multi-channel and simulation results of multi-channel time-interleaved sampling switches. The back-end analog-to-digital converter will be introduced and divided into two parts which is successive approximation analog to digital converter and pipeline analog to digital converter discretely. A 10-bit 100MS/s SAR ADC with ENOB 9.92 and perfect DNL、INL. The average power consumption is 2.42mW and the average energy consumption is 25fJ each conversion. The circuit structure of pipeline analog to digital converter is mainly comprised of Flash ADC and switch-cap sub-DAC

目錄
中文摘要
ABSTRACT(英文摘要)
目錄
表目錄
圖目錄
第一章:簡介以及研究背景介紹
1.1 論文章節架構介紹
1.2 類比數位轉換器參數
1.2.1 最小有效位元(Least Signification Bit)
1.2.2 微分線性度(Differential Nonlinearity)
1.2.3 遺失碼(Missing Codes)
1.2.4 積分線性度(Integral Nonlinearity)
1.2.5 偏移偏差(Offset)
1.2.6 增益誤差(Gain Error)
1.2.7 訊號雜訊比(Signal-to-Noise Ratio)
1.2.8 訊號雜訊諧波比(Signal-to-Noise and Distortion Ratio)
1.2.9 有效位元數(Effective Number of Bits)
1.2.10 SFDR(Spurious Free Dynamic Range)
1.2.11 總諧波失真(Total Harmonic Distortion)
第二章:連續漸進式類比數位轉換器
2.1連續漸進式類比數位轉換器概念及原理
2.1.1連續漸進式類比數位轉換器系統架構
2.1.2連續漸進式類比數位轉換器演算法
2.2 連續漸進式類比數位轉換器子電路介紹
2.2.1 取樣保持電路(Sample and Hold)簡介及其設計考量
2.2.2 取樣保持電路(Sample and Hold)介紹
2.2.3比較器(Comparator)
2.2.4 電容式數位類比轉換器(Capacitor DAC)
2.3 連續漸進式類比數位轉換器模擬結果
第三章:導管式類比數位轉換器
3.1導管式類比數位轉換器系統架構
3.2導管式類比數位轉換器子電路介紹
3.2.1 取樣保持電路(Sample-and-Hold Circuit)
3.2.2 子類比數位轉換器(sub-ADC)
3.2.3 倍乘式數位類比轉換器(MDAC)
3.2.4 數位錯誤更正電路
3.3 250MS/s 10位元電荷域導管式類比數位轉換器電路介紹
3.3.1 高速導管式類比數位轉換器的限制因素
3.3.2 子類比數位轉換器電路架構(sub-ADC)
3.3.3 電荷域子數位類比轉換器架構(Sub-DAC)
3.3.4 數位錯誤更正電路架構
3.4 250MS/s 10位元電荷域導管式類比數位轉換器模擬結果
第四章:多通道時間交錯式類比數位轉換器
4.1 多通道時間交錯技術的非理想效應
4.1.1 Offset mismatch
4.1.2 Gain mismatch
4.1.3 Timing mismatch
4.2多通道時間交錯式類比數位轉換器電路介紹
4.2.1靴帶電路模擬結果
4.3 比較表
第五章: 結論及未來發展
參考文獻
 
表目錄
表2.1十位元連續漸進式類比數位轉換器模擬結果
表4.1靴帶電路模擬結果
表4.2四通道時間交錯式類比數位轉換器模擬結果

[1] S.Hashemi and B.Razavi, “A 10-Bit 1-GS/s CMOS ADC with FOM=70 fJ/Conversion,” IEEE CICC, Sep. 2012.
[2] A. Verma and B. Razavi, “A 10-Bit 500-MS/s 55-mW CMOS ADC,”IEEE J.Solid-State Circuits, vol. 44, no. 11, pp. 3039–3050, Nov. 2009.
[3] M. Anthony et al., “A process-scalable low-power charge-domain 13-bit pipeline ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun.2008, pp. 222–223.
[4] W. FREY, “Bucket-brigade device with improved charge transfer”, IET Electronics Letters, Vol.9, No.25, pp.588–589, 1973.
[5] I. Ahmed, J. Mulder, and D. A. Johns, “A low-power capacitive charge pump based pipelined ADC,” IEEE J. Solid-State Circuits, vol. 45, no.5, pp. 1016–1027, May 2010.
[6] D. W. Cline and P. R. Gray, “A power optimized 13-b 5 M Samples/s pipelined analog-to-digital converter in 1.2um CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294–303, Mar. 1996.
[7] C.H. Cheol, K.Y. Ju, K.W. Joo, et al., “A 10b 120 MS/s 108mW 0.18μm CMOS ADC with a PVT-insensitive current reference”, Analog Integrated Circuits and Signal Processing, Vol.61,No.58, pp.115–121, 2009.
[8] C.C. Liu, et al, ‘‘A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,’’ IEEE J. Solid-State Circuits, vol.45, no. 4, Apr. 2010, pp. 731-740.
[9] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, “A 10-b 50 MS/s 820-uW SAR ADC with on-chip digital calibration,” IEEE ISSCC Dig. Tech. Papers, 2010, pp. 384–385.
[10] C.C. Liu, et al., “A 1V 11fJ/conversion-step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS,” IEEE Symposium on VLSI Circuits, pp. 241-242, June 2010.
[11] S. M. Chin, C. C. Hsieh, C. F. Chiu, and H. H. Tsai, "A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application," IEEE Int. Symp. on Circuits and Systems, 2010, pp. 1575-1578.
[12] S. M. Louwsma, A. J. M. Van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13um CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778–786, Apr. 2008.
[13] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K.Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 261–271, Mar. 2001.
[14] K. C. Dyer et al. “A digital background calibration technique for time-interleaved analog-to-digital converters”, IEEE J. Solid-State Circuits, vol. 33, Dec. 1998, pp. 1904-1911.
[15] Jamal, S.M. et al. “A 10-b 120-msample/s time-interleaved analog-to-digital converter with digital background calibration”, IEEE J. Solid-State Circuits, vol.37, Dec. 2002, pp. 1618- 1627.
[16] K. C. Dyer et al. “An analog background calibration technique for time-interleaved analog-to-digital converters”, IEEE J. Solid-State Circuits, vol. 33, Dec. 1998, pp. 1912- 1919.
[17] J. Li and U.-K. Moon, “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp. 531–538, Sep. 2003
[18] C.-Y. Wang and J.-T. Wu, “A background timing-skew calibration technique for time-interleaved analog-to-digital converters,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 4, pp. 299–303, Apr. 2006.