隨著科技的發展，無線通訊技術大幅改善人們的生活，4G無線通訊提供了極高的資料傳輸速度，讓人們在通話時能夠享有更高的品質甚至透過視訊面對面通話，網路傳輸的速度能夠讓人們使用攜帶型裝置觀看高畫質的影片或是直播節目，而在這些美好的應用背後，類比數位轉換器是系統中不可或缺的，它是唯一能夠將大自然訊號轉換成數位訊號的電路，讓大自然訊號經由數位訊號處理得到更多的好處。現今許多不同類型的類比數位轉換器持續提升效能，往更高的解析度或是更高的速度發展，但是連續漸進式類比數位轉換器卻是最近較為流行的，因為它本身的面積與功耗較小，能夠藉由製程縮小獲得更快的速度，比其他類型的類比數位轉換器更有優勢。
本論文實現了一個高速帶冗餘位連續漸進式類比數位轉換器，在每秒一億次取樣的速度以及10位元的解析度下，考量電容不匹配與數位類比轉換器的穩定時間兩項非理想效應，計算出帶冗餘位演算法中每次切換的基底，這個10位元每秒一億次取樣的連續漸進式類比數位轉換器利用台積電65奈米的CMOS製程來設計，操作電壓為1V，軌對軌輸入訊號的振幅為1.9V，模擬結果中訊號與雜訊諧波比可達到62.09dB，相當於有效位元為10.02，DNL為+0.6/-0.4 LSB，INL為+0.63/-0.4 LSB，平均消耗功率為2.02 mW，整體面積約為0.28785 mm2。

The development of Wireless communication technology has greatly improved our lives. 4G communication systems provide high data transmission speeds. It allows people to communicate with high-quality voice or even video calls. Behind the amazing applications, the high speed ADC is an essential block in the system. It’s the only block that can convert the nature signal to digital signal. There many types of ADC keep improving their ability. But the SAR ADC is more popular in recent years, because it takes a lot of advantage of technology scales.
In the thesis, we have proposed a high speed SAR ADC with redundancy algorithm. The algorithm combines the criterion of capacitor mismatch and DAC settling time. The radix of each stage can be calculated precisely under 100 million samples per second. The 10 bits SAR ADC is implemented in a TSMC 65 nm CMOS process with 1V supply voltage. The full rail-to-rail input swing is 1.9V peak to peak. This design achieve signal to noise and distortion ratio of 62.09dB, equivalent to the effective number of bits 10.02.The peak DNL values are -0.4 to +0.6 LSB and the peak INL values are -0.4 to +0.63 LSB. The average power consumption is 2.02mW.

目錄
中文摘要 i
Abstract(英文摘要) ii
目錄 iii
圖目錄 vii
表目錄 x
第一章 簡介 1
1.1 研究動機(Motivation) 1
1.2 論文章節組織 2
第二章 研究背景以及相關研究介紹 3
2.1 奈奎斯特取樣類比數位轉換器 3
2.1.1 連續漸進式類比數位轉換器(SAR ADC) 3
2.1.2 管線式類比數位轉換器(Pipeline ADC) 5
2.1.3 快閃式類比數位轉換器(Flash ADC) 6
2.2 類比數位轉換器參數 7
2.2.1 專有名詞 7
2.2.1.a 解析度(Resolution) 7
2.2.1.b 取樣率(Sampling Rate) 7
2.2.1.c 量化誤差(Quantization Error) 7
2.2.1.d 最小解析度(Least Signification Bit) 9
2.2.2 靜態特性 10
2.2.2.a 偏差(Offset) 10
2.2.2.b 增益誤差(Gain Error) 10
2.2.2.c 差動非線性度(Differential Nonlinearity) 11
2.2.2.d 積分非線性度(Integral Nonlinearity) 11
2.2.2.e 遺失碼(Missing Codes) 12
2.2.3 動態特性 13
2.2.3.a 訊號與雜訊比(Signal-to-Noise Ratio) 13
2.2.3.b 訊號與雜訊諧波比(Signal-to-Noise and Distortion Ratio) 13
2.2.3.c 有效位元數(Effective Number of Bits) 13
2.2.3.d 無雜訊動態範圍(Spurious Free Dynamic Range) 14
2.2.3.e 動態範圍(Dynamic Range) 14
2.2.3.f 總諧波失真(Total Harmonic Distortion) 14
2.3 連續漸進式類比數位轉換器(SAR ADC) 15
2.3.1 電荷重新分布SAR ADC(Charge Redistribution SAR ADC) 15
2.3.2 電容切換演算法 16
2.3.2.a 傳統式電容切換演算法(Conventional switching algorithm) 17
2.3.2.b 單調性電容切換演算法(Monotonic switching algorithm ) 18
2.3.2.c 電容拆半切換演算法(Split-capacitor switching algorithm) 19
2.3.3 單端與雙端概念 21
2.3.4 同步與非同步概念 22
第三章 帶冗餘位連續漸進式類比數位轉換器 23
3.1 高解析度與高速度的困難 23
3.1.1 高解析度 23
3.1.2 高速度 24
3.2 帶冗餘位演算法 25
3.2.1 非二分法搜尋(Non-binary search) 25
3.2.2 忍錯範圍 26
3.2.3 基底γ (radix) 27
3.2.4 γ的選定 28
3.2.4.a 電容不匹配 28
3.2.4.b DAC穩定時間 30
3.2.5 M的選定 32
3.3 65奈米10位元每秒一億次取樣帶冗餘位演算法實作 34
第四章 帶冗餘位連續漸進式類比數位轉換器之設計 38
4.1 取樣及保持電路(Sample and Hold) 38
4.1.1 電路原理 38
4.1.2 設計考量 38
4.1.2.a 頻寬(Bandwidth) 39
4.1.2.b 熱雜訊(Thermal noise) 39
4.1.2.c 電荷注入效應(Charge injection) 40
4.1.2.d 時脈饋入效應(Clock feedthough) 41
4.1.2.e 非線性電阻(Non-linear Resistance) 41
4.1.3 電路實作 42
4.1.4 模擬結果 44
4.2 比較器(Comparator) 47
4.2.1 電路原理 47
4.2.2 設計考量 48
4.2.2.a 操作速度(Speed) 48
4.2.2.b 偏移(Offset) 48
4.2.2.c 準確度(Accuracy) 48
4.2.2.d 回饋雜訊(Kick-back noise) 48
4.2.2.e 功率消耗(Power consumption) 48
4.2.3 電路實作 49
4.2.4 模擬結果 50
4.3 電容矩陣(Capacitor Array) 52
4.3.1 電路實作 52
4.4 連續漸進式邏輯電路(SAR Logic) 54
4.4.1 內部時序邏輯(Timing logic) 54
4.4.2 控制邏輯(control logic) 55
4.4.3 同步非同步控制邏輯(synchronous asynchronous control logic) 57
4.5 連續漸進式類比數位轉換器(SAR ADC)佈局圖 58
4.6 連續漸進式類比數位轉換器模擬結果 59
4.6.1 動態參數 59
4.6.2 靜態參數 61
第五章 結論與未來發展 63
參考文獻 64

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