台灣的半導體產業發展已趨成熟，淬煉出在全球半導體產業獨樹一格的垂直分工經營模式，屬於供應鏈後段的IC測試產業在代工能力或產值規模上在全球皆排名首位。
各整合元件大廠(Integrated Device Manufacturer）競爭激烈，由於成本的考量，成熟產品的測試時間呈現縮短之趨勢，因而測試產業面臨著如何維持生產效率之問題。以工廠而言，產能效率的高低，就是競爭力的衡量指標，提昇其生產效率，對目前測試產業來說，已是一個相當重要的課題。
由於短測試時間之限制，機台浪費許多等待著測試的時間。本研究在影響測試生產效率的各因素中，針對短測試時間之機台於測試間之等待時間(Index time)的影響因素進行分析，以提升機台效率產出做出具體的探討，並以台灣某半導體封裝測試廠為實證，使用要因分析圖與實驗設計法找出影響IC測試機Index time的顯著影響因子，計算出造成機台效率之損失，進而提出改善方案，提高生產效率，平均減少短測試時間19%的minimum time時間，意即增加了19%產出。

The semiconductor industry in Taiwan has become a mature industry, whose industry structure is a unique vertical separation model compared to that of the other countries. Taiwan’s IC testing business, which belongs to the downstream part of the semiconductor supply chain, is top-notch in the world in terms of the OEM capability and the scale of output value.
It is quite competitive nowadays among integrated device manufactures. Considering the cost, the testing time in mature products has been significantly reduced, which means IC testing companies need to improve production efficiency to keep their competitiveness. For factories, production capability is a key competitiveness index so that how to improve production efficiency is a very important subject for IC testing companies.
Machines easily become idle due to short testing time. This research focused on the factors which had influence on the idle time in short testing time machines and tried to improve production efficiency of machines. In addition, the research was applied to a semiconductor testing company in Taiwan. Causes and effects chart and design of experiment were used to look for the significant factors affecting idle time of IC testing machines so that the capacity loss can be minimized. According to the factors, some proposals were put forward to raise the production efficiency, average reduction 19% of the short test time’s minimum time which means an increase of 19 percent of output.

摘要 i
Abstract ii
致 謝 iii
目錄 iv
表目錄 vi
圖目錄 vii
1. Introduction 1
2. Literature Review 3
2.1、 產能方面 3
2.2、 設備方面 4
3. Problem Definitions 5
3.1、 半導體測試概述 5
3.2、 記憶體成品測試流程 5
3.3、 IC測試設備簡介 7
3.4、 Index time 9
4. Causes Analysis and Design of Experiments 11
4.1、 影響Index time原因分析 11
4.2、 Design of Experiments 13
4.2.1、 實驗因子篩選 14
4.2.2、 資料收集與分析 16
4.2.3、 期望效率狀況 17
5.機台改善流程 19
5.1、 維修DUT off 19
5.2、 增加Test Tray 22
5.3、 Index time降低所產生之效益 22
5.4、 機台改善流程 23
5.5、 實證結果分析 26
6.Conclusions 27
6.1、 Limitations 27
6.2、 Future Research 28
References 29
附錄:影響Index time因子分析 33
附錄1.1、 測試時間 33
附錄1.2、 Soak time 34
附錄1.3、 Unsoak time 35
附錄1.4、 Test Tray 數量 36
附錄1.5、 DUT off rate 38
附錄1.6、 產品良率與分BIN問題 40
附錄1.7、 Load/Unload 速度 43

1. 彭茂榮、楊瑞臨, (2013), 台灣半導體產業與運用年鑑,財團法人工業技術研究院.
2. 何宗憲、陳建良、張進群、陳俊杰、曾淑美、何土城、鄧玉春, (1998), IC測試與製程簡介, 機械工業雜誌. 189期, 189-203頁.
3. 李嘉柱、李佳穎, (1999),半導體後段廠之現場生產流程與作業管制條件分析, 機械工業雜誌, 109~111頁.
4. 陳建良、楊朝龍、吳明穎、陳哲豪、林純如、彭郁惠, (2013), 巨量資料於IC測試產業之應用機會, 中國工業工程學會102年度年會暨學術研討會.
5. 陳建良、項衛中、孫正儒、陳俊傑, (2005), 半導體成品測試廠産能規劃研究，中原學報（自然科學及工程系列）, 33卷1期, 57–70頁.
6. Ahmed, I., & Fisher, W. W. (1992). Due Date Assignment, Job Order Release, and Sequencing Interaction in Job Shop Scheduling*. Decision Sciences, Volume 23, Issue 3, Pages 633–647.
7. Bard, J.F., Yumin Deng, Chacon, R. & Stuber, J. (2010), Midterm Planning to Minimize Deviations From Daily Target Outputs in Semiconductor Manufacturing, Semiconductor Manufacturing, Volume 23, Issue 3, Pages 456 – 467.
8. Bergamaschi, D., Cigolini, R., Perona, M. & Portioli, A. (1997), Order review and release strategies in a job shop environment: A review and a classification, International Journal of Production Research, Volume 35, Issue 2, pages 399-420.
9. Chan, F. T. S., Lau, H. C. W., Ip, R. W. L., Chan, H. K., & Kong, S. (2005), Implementation of total productive maintenance: A case study, International Journal of Production Economics, Volume 95, Issue 1, Pages 71–94.
10. Chien, C.F., Wang, H.J. & Wang, M. (2007), A UNISON Framework for Analyzing Alternative Strategies of IC Final Testing for Enhancing Overall Operational Effectiveness, International Journal of Production Economics, Volume 107, Pages 20–30.
11. Chou, F.D., Wang, H.W. & Chang, P.C. (2008), A simulation annealing approach with probability matrix for semiconductor dynamic scheduling problem, Expert Systems with Applications, Volume 35, Issue 4, Pages 1889–1898.
12. Christy, D. P., & Kanet, J. J. (1990), Manufacturing Systems with Forbidden Early Shipment: Implications for Choice of Scheduling Rules, International Journal of Production Research, Volume 28, Issue 1.
13. Cigolini, R., Perona, M. & Portioli, A. (1998), Comparison of Order Review Techniques in a Dynamic and Uncertain Job Shop Environment, International Journal of Production Research, Volume 36, Issue 11, Pages 2931-2951.
14. Huang, S. H., Dismukes, J. P., Shi, J., Su, Q. I., Razzak, M. A., Bodhale, R., & Robinson, D. E. (2003), Manufacturing productivity improvement using effectiveness metrics and simulation analysis, International Journal of Production Research, Volume 41, Issue 3, Pages 513-527.
15. Ishikawa, K. (1986). Guide to Quality Control. UNIPUB/Kraus International, White Plains, New York.
16. Jonsson, P., & Lesshammar, M. (1999), Evaluation and Improvement of Manufacturing Performance Measurement Systems — The Role of OEE, International Journal of Operations & Production Management, Volume 120 Issue 1, Pages 55 – 78.
17. Leachman, R. C., & Carmon, T. F. (1992), On Capacity Modeling For Production Planning With Alternative Machine Types, IIE Transaction, Volume 24, Issue 4, Pages 62-72.
18. Leachman, R.C. (1997), Closed-loop measurement of equipment efficiency and equipment capacity, Semiconductor Manufacturing, IEEE Transactions, Volume 10, Issue 1, Pages 84-97.
19. Lin, J. T., Wang, F. K., & Lee, W. T. (2004), Capacity-constrained scheduling for a logic IC final test facility, International Journal of Production Research, Volume 42, Issue 1, Pages 79-99.
20. Matsuura, H., Tsubone, H., & Kataoka, K. (1995), Comparison between Simple Infinite Loading Considering a Workload Status under Uncertainty in Job Operation Times, International Journal of Production Economics, Volume 40, Pages 45-55.
21. Muchiri, P., & Pintelon, L. (2008), Performance measurement using overall equipment effectiveness (OEE): literature review and practical application discussion, International Journal of Production Research, Volume 46, Issue 13, Pages 3517-3535.
22. Park, G.J. (2007), Analytic methods for design practice, Springer, Germany.
23. Swaminathan, J. M. (2000), Tool capacity planning for semiconductor fabrication facilities under demand uncertainty, European Journal of Operational Research, Volume 120, Issue 3, Pages 545–558.
24. Wang, K. J., & Lin, S. H. (2002), Capacity expansion and allocation for a semiconductor testing facility under constrained budget, Production Planning & Control, The Management of Operations, Volume 13, Issue 5, Pages 429-437.
25. Wu, M. C., & Chang, W. J. (2007), A Short-term capacity trading method for semiconductor fabs with partnership, Expert System With Application, Volume 33, Issue 2, Pages 476–483.