現今電子產品發展朝向高功率、高密度、可靠度佳以及微小化等特性發展，在眾多的封裝結構中晶圓級晶片尺寸封裝(Wafer Level Chip Size Packaging, WLCSP)同時具備了以上特性。對於WLCSP而言由於其結構在晶片及錫球間具有緩衝層結構設計，緩衝層可減少錫球之受力並延長其壽命，因此不同於覆晶封裝(Flip Chip Packaging)，WLCSP是不需要充填底膠(underfill)結構的。少了底膠的保護，若結構設計不良，則WLCSP封裝會因為晶片與基板之間熱膨脹係數不匹配造成過高的熱應變及熱應力而使得錫球接點提早破壞。通常評估WLCSP可靠度的測試實驗會花費許多時間及金錢，若能將WLCSP準確以有限元素法分析，其模擬結果將可取代實驗，並大幅縮短產品研發之時程。本研究將以有限元素模擬法對WLCSP進行分析探討。
近年來為了降低可靠度測試時間，將負載設定成更嚴苛的環境，使得測試載具提前失效以達成加速測試之目的。根據JEDEC標準測試規範，常用的溫度測試範圍為-40°C到125°C，因此本研究採用此範圍進行模擬分析。在加速熱循環負載測試中，溫度通常都超過焊錫材料熔點絕對溫度(K)的三分之一，因此在此過程中即會發生較為顯著的潛變效應，造成潛變應變的累積。
對於加速熱循環負載型式而言，提高升降溫速率對於縮短測試時間是常被使用的方法。然而升降溫速率提高會使得材料應變率上升，造成材料強度的變化，而潛變也會因升溫速率的提高，使得在整體溫度循環中之升降溫段時間減少，造成較少的潛變應變累積。由於潛變應變累積較小伴隨鬆弛現象的降低，使得在結束升降溫段有較高之應力，高應力就容易使得材料在熱循環過程中進入塑性區。由此可知升溫速率的改變對於可靠度具有一定程度的影響。此外，在溫度循環過程中持溫時間對於可靠度的影響也非常重要，因為當持溫時間越長則產生的潛變應變越多，使得錫球壽命降低，因此如何對其行為進行精準的評估是相當重要的。
本研究中將以兩種不同理論，分析在加速熱循環條件下潛變及塑性應變之相關行為，這兩種理論分別為Anand 模型以及Garofalo 雙曲正弦模型搭配Chaboche動態硬化模型來描述潛變及塑性應變行為。由分析結果可知使用這兩組理論進行分析將會得到相同的應變累積趨勢。
其中本研究中還探討了兩種不同壽命預估模型在不同升降溫速率之可靠度評估，其中兩種壽命預估模型分別為Coffin-Manson 應變法以及Darveaux能量密度法，經由模擬結果顯示在改變升降溫速率時等效非彈性應變增量不明顯，將此結果代入Coffin-Manson 應變法無法呈現實驗結果的趨勢，但是將應變能密度結果代入Darveaux能量密度法模型，其趨勢則與實驗結果相符。此外，若加速熱循環條件為固定升降溫速率及改變持溫時間，則可以發現將其結果分別代入Coffin-Manson 應變法以及Darveaux能量密度法皆可獲得與實驗結果相同的趨勢。
對於Norris-Landzberg所提出之加速因子(Acceleration Factor, AF)而言未將潛變效應納入考量，因此若將改變升降溫速率之結果代入此公式將會預估出違背實驗及模擬結果。本研究最後將提出修正型之加速因子公式並將潛變納入考量，使其計算結果符合實驗及模擬結果。

Nowadays, electronic packaging has developed to achieve high power, high I/O, good reliability performance and small form factor characteristics. Among the various packages have been adopted by industry, Wafer Level Chip Size Packaging (WLCSP) fulfills above demands. Unlike flip chip packaging, WLCSP does not need underfill protection since it possesses a soft stress buffer layer between silicon chip and solder bump, the buffer layer can reduce the stress/strain in solder joint and prolong its lifetime. However, no underfill protection induced the high stress/strain which is caused by coefficient of thermal expansion mismatch (CTE) in thermal loading. This effect allows WLCSP failure more easily. In general, using experiments to assess reliability of WLCSP will take much time and money, so the finite element method and design-on-simulation technology have been widely used for predicting the thermal fatigue life of packaging under thermal cycling loading condition. If the simulation results are exact to match the experiments, this simulation can substitute the experiments to progress some analysis such as parameter designs, fatigue life prediction, etc. Using finite element method would spend less time than conduct some experiments, so this research gives finite element method of WLCSP to analyze creep effect and discuss various thermal cycling loading conditions.
In order to reduce the development time and ensure the reliability quality of electronic packaging, the Accelerated Thermal Cycling Test (ATC) is a standard method which is currently used to characterize the reliability performance of electronic packaging. The most commonly used temperature range for commercial electronic products is from -40°C to 125°C, and within a predefined temperature range the creep effect is more significant in the solder material because the homologous temperature is excessed to 0.33 Tm (in K) in the thermal cycling loading. According to the simulation result, it can be found the creep effect is the main factor that caused the solder to failure.
The increase in the ramp rate of the thermal cycling loading is often used to reduce test duration, but increase in the ramp rate causes the material to change its stress/strain properties. In addition, creep effect becomes smaller in the ramp section of thermal cycling because it allows lesser time in the ramp section of thermal cycling. Due to increasing ramp rate, it causes a less creep effect, so the stress relaxation effect also becomes less. Because of the less stress relaxation effect, it makes the materials have more stress at the end of ramp section that allows the materials to produce plastic strain more easily. To sum up, changing the ramp rate in the thermal cycling loading influences the reliability of electronic packaging. On the other hand, the dwell time of thermal cycling also affects the reliability of materials because increases in the dwell time that causes more creep strain and has less fatigue cycles in the solder material. According to the above discussion, it is very important to use an exact simulation method to assess the reliability of electronic packaging.
In this study, the Anand Model and the Garofalo Hyperbolic Sine Model with Chaboche Kinematic Hardening Model are used to simulate creep and plasticity behavior in the simulation process. The results of simulation indicates that both of them have the same tendency during thermal cycling loading.
There are two standard methods to calculate the predict fatigue cycles such as Coffin-Mason strain based model and Darveaux energy based model. The results of simulation demonstrate that the incremental inelastic strain is changed insignificantly, so the fatigue cycle can’t coincide with the experimental results which are calculated by using Coffin-Mason strain based model. In addition, the incremental energy density is increased when the ramp rate is increased. Substituting this results to Darveaux energy based model would get the life prediction cycles which is agreed with the experiment results. Moreover, in the case of fixed ramp rate and varied the dwell time, the life prediction cycles which are calculated by both models and have the same tendency of the life predicted cycles.
In Norris-Landzberg Acceleration Factor Model, it doesn’t consider creep effect in this formula, so it will predict a violation result when using the experimental data which are progressed on fixed dwell time and various ramp rate in thermal cycling test. Finally, the modified AF formula which considers the creep effect will be proposed. As a result, the life prediction cycle which is calculated by the modified AF formula is corresponded with all of experimental results.

目錄
摘要 I
Abstract IV
目錄 VII
圖目錄 X
表目錄 XIV
第一章 緒論 1
1.1 研究動機 1
1.2 文獻回顧 4
1.3 研究目標 17
第二章 基礎理論 19
2.1 有限元素法基礎理論 19
2.1.1 線彈性有限元素法理論 20
2.1.2 材料非線性理論 24
2.1.3 數值方法及收斂準則 28
2.2 等向硬化法則(Isotropic Hardening Rule) 30
2.3 動態硬化法則(Kinematic Hardening Rule) 31
2.4 Garofalo-Arrhenius 潛變理論 32
2.5 Anand 模型 33
2.6 Chaboche 模型 36
2.7 封裝結構可靠度預測方法 38
2.7.1 Coffin-Mason 應變法 38
2.7.2 Darveaux 能量密度法 38
2.8 Norris-Landzberg加速因子公式 39
第三章 WLCSP溫度負載實驗及有限元素模型之建立 41
3.1 WLCSP於溫度負載測試實驗 41
3.2 WLCSP幾何尺寸及有限元素模型建立 44
3.3 有限元素模型基本假設 46
3.4 材料參數設定 46
3.5 邊界條件及負載設定 49
第四章 分析結果與討論 51
4.1 潛變及塑性行為分析 51
4.1.1 潛變應變及塑性應變 51
4.1.2 潛變應變能密度及塑性應變能密度 52
4.2 von Mises 應力結果分析 53
4.2.1 改變升降溫速率之影響 60
4.2.2 改變持溫時間之影響 61
4.3 非彈性應變增量模擬結果 61
4.4 非彈性應變能密度增量模擬結果 66
4.5 實驗與壽命預估模型驗證 69
4.5.1 Coffin-Mason 應變法 69
4.5.2 Darveaux 能量密度法 71
4.6 預估不同持溫時間及升降溫速率之壽命 72
4.7 加速因子公式之探討 77
4.7.1 加速因子公式之修正式 77
4.7.2 模擬與Norris-Landzberg加速因子公式之曲線擬合 79
4.7.3 實驗與加速因子公式之驗證 80
第五章 結論及未來展望 82
參考文獻 89
 
圖目錄
圖 1-1 封裝技術演進圖( 為晶片尺寸大小)[1] 4
圖 1-2 溫度循環負載圖[3]。(a) 整體循環圖、(b)低升溫速率及低持溫時間負載圖、(c) 高升溫速率及高持溫時間負載圖。 6
圖 1-3 錫銀焊料在高升降溫速率下不同循環數之表面破壞累積圖[3]。(a)0循環數、(b)250循環數、(c)500循環數、(d)1,000循環數 6
圖 1-4 錫銀焊料在固定1,000循環數下不同升溫速率之表面破壞情形[3]。(a)低升溫速率、(b)高升溫速率 7
圖 1-5 壽命時間對於不同升降溫速率之分佈情形[4] 8
圖 1-6 改變升降溫速率錫球之破壞情形[4](左圖為熱衝測試、右圖溫度循測試) 8
圖 1-7 對於不同升降溫條件下潛變應變增量分佈圖[6] 10
圖 1-8 熱衝擊及熱循環測試下，經過一個循環之應變能密度增量情形[10]。(固定持溫時間為15分鐘) 12
圖 2-1 材料在彈性區受到一固定負載，在 卸載之應變關係圖[23] 24
圖 2-2 材料受到一固定負載且此負載超過材料降伏強度，並在 卸載所對應之應變關係圖[23] 25
圖 2-3 潛變曲線圖 26
圖 2-4 材料在時間 卸載後，所對應之回復現象圖[23] 27
圖 2-5 材料受到固定應變，對應之應力發生鬆弛現象圖[23] 27
圖 2-6 Full Newton-Raphson 非線性疊代示意圖 29
圖 2-7 (a)等向硬化應力-應變關係圖，(b)等向硬化降伏面變化圖 30
圖 2-8 (a)動態硬化應力-應變關係圖，(b)動態硬化降伏面變化圖 31
圖 2-9 潛變變形機制圖[29] 32
圖 3-1 WLCSP測試載具 41
圖 3-2 Espec-TCC 150 42
圖 3-3 WLCSP實驗結果之韋伯分佈圖 43
圖 3-4 WLCSP模型剖面示意圖 45
圖 3-5 斜對角線取二分之一對稱有限元素模型圖 45
圖 3-6 Anand Model於96.5Sn/3.5Ag材料曲線圖 48
圖 3-7 Hyperbolic Sine Model於96.5Sn/3.5Ag材料曲線圖 49
圖 3-8 邊界條件設定示意圖 50
圖 4-1 模擬結果之錫球非彈性應變分布圖 54
圖 4-2 實驗結果破壞情形SEM圖[41] 54
圖 4-3 升溫速率11°C/min且持溫時間為5分鐘時von Mises stress時間歷程圖 55
圖 4-4 升溫速率11°C/min且持溫時間為10分鐘時von Mises stress時間歷程圖 56
圖 4-5 升溫速率11°C/min且持溫時間為15分鐘時von Mises stress時間歷程圖 56
圖 4-6 升溫速率16.5°C/min且持溫時間為5分鐘時von Mises stress時間歷程圖 57
圖 4-7 升溫速率16.5°C/min且持溫時間為10 分鐘時von Mises stress時間歷程圖 57
圖 4-8 升溫速率16.5°C/min且持溫時間為15分鐘時von Mises stress時間歷程圖 58
圖 4-9 升溫速率33°C/min且持溫時間為5分鐘時von Mises stress時間歷程圖 58
圖 4-10 升溫速率33°C/min且持溫時間為10分鐘時von Mises stress時間歷程圖 59
圖 4-11 升溫速率33°C/min且持溫時間為15分鐘時von Mises stress時間歷程圖 59
圖 4-12 Anand Model在不同升降溫速率及持溫時間下非彈性應變增量圖 64
圖 4-13 Hyperbolic Sine Model with Chaboche Kinematic Hardening Model在不同升降溫速率持溫時間下非彈性應變增量圖 65
圖 4-14 Anand Model在不同升降溫速率下應變能密度增量圖 68
圖 4-15 Hyperbolic Sine Model with Chaboche Kinematic Hardening Model在不同升降溫速率下應變能密度增量圖 68
 
表目錄
表 3-1 WLCSP各結構尺寸 42
表 3-2 WLCSP實驗結果 42
表 3-3 WLCSP二維對稱有限元素模型尺寸 45
表 3-4 有限元素模型之線性材料參數 47
表 3-5 96.5Sn/3.5Ag之Anand Model之材料參數設定 47
表 3-6 96.5Sn/3.5Ag之Hyperbolic Sine Model之材料參數設定 48
表 3-7 96.5Sn/3.5Ag於不同溫度之楊氏模數及降伏強度 49
表 3-8 溫度負載形式設定 50
表 4-1 各負載下之潛變應變及塑性應變穩定增量 52
表 4-2 不同負載下之潛變應變能密度穩定增量及塑性應變能密度穩定增量 53
表 4-3 Hyperbolic Sine Model with Chaboche Kinematic Hardening Model在固定持溫時間為10分鐘，改變升降溫速率下之非彈性應變於各負載段之增量情形 64
表 4-4 將兩種模擬結果代入Coffin-Mason與實驗結果比較 69
表 4-5 將兩種模擬結果代入Darveaux 應變能密度法並與實驗結果比較 71
表 4-6 在不同溫度負載下之模擬結果代入Coffin-Mason 應變法之壽命數 73
表 4-7 在不同溫度負載下之模擬結果代入Darveaux 能量密度法之壽命數 73
表 4-8 使用三組條件之模擬壽命數及曲線擬合值 79
表 4-9 驗證(4 9)式對於錫銀銅焊料於不同負載之實驗 80

[1] R. Tummala, Fundamentals of Microsystems Packaging: McGraw-Hill Professional; 1st edition, 2001.
[2] J. H. Lau, S. W. R. Lee, and C. Chang, “Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis,” Journal of Electronic Packaging, Vol. 122, pp. 311-316, 2000.
[3] J. G. Lee, and K. N. Subramanian, “Effects of TMF heating rates on damage accumulation and resultant mechanical behavior of Sn–Ag based solder joints,” Microelectronics Reliability, Vol. 47, pp. 118-131, 2007.
[4] T. T. Mattila, H. Xu, O. Ratia, and M. Paulasto-Krockel, “Effects of thermal cycling parameters on lifetimes and failure mechanism of solder interconnections,” Electronic Components and Technology Conference (ECTC) 60th, Las Vegas, Nevada, USA., June 1-4, 2010.
[5] K. C. Wu, S. Y. Lin, and K. N. Chiang, “Investigation of strain rate effect on lifetime performance of wafer level CSP under different thermal cycling loading rate,” IMPACT, Taipei, Taiwan, Oct 22-24 2014.
[6] Y. S. Chan, and S. W. R. Lee, “Detailed investigation on the creep damage accumulation of lead-free solder joints under accelerated temperature cycling,” Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE). 11th, France, April 26-28 2010.
[7] J. Lau, W. Danksher, and P. Vianco, “Acceleration models, constitutive equations, and reliability of lead-free solders and joints,” Electronic Components and Technology Conference, Proceedings 53rd, New Orleans, Louisiana, USA May 27-30 2003.
[8] J. Lau, and W. Dauksher, “Effects of Ramp-Time on the Thermal-Fatigue Life of SnAgCu Lead-Free Solder Joints,” Electronic Components and Technology Conference 55th, Lake Buena Vista, FL, USA May 31 -June 3 2005.
[9] R. H. Hong, and J. Wang, “Effect of thermal shock profile on solder joint of WLCSP,” Electronic Packaging Technology and High Density Packaging (ICEPT-HDP) 12th, Shanghai, China, Aug 8-11, 2011.
[10] X. Fan, G. Raiser, and V. S. Vasudevan, “Effects of Dwell Time and Ramp Rate on Lead-Free Solder Joints in FCBGA Packages,” Electronic Components and Technology Conference 55th, Lake Buena Vista, FL, USA, May 31-June 3, 2005.
[11] S. Sahasrabudhe, E. Monroe, S. Tandon, and M. Patel, “Understanding the effect of dwell time on fatigue life of packages using thermal shock and intrinsic material behavior,” Electronic Components and Technology Conference 53rd, New Orleans, Louisiana, USA, May 27-30, 2003.
[12] S. C. Chaparala, B. D. Roggeman, J. M. Pitarresi, B. G. Sammakia, J. Jackson, G. Griffin, and T. McHugh, “Effect of geometry and temperature cycle on the reliability of WLCSP solder joints,” IEEE Transactions on Components and Packaging Technologies, Vol. 28, pp. 441-448, 2005.
[13] C. J. Zhai, Sidharth, and R. Blish, II, “Board level solder reliability vs. ramp rate & dwell time during temperature cycling,” Reliability Physics Symposium Proceedings 41st, Dallas, Texas 30 March-4 April, 2003.
[14] X. Yan, and G. Li, “Study of thermal fatigue lifetime of fan-in package on package (FiPoP) by finite element analysis,” Electronic Packaging Technology & High Density Packaging Shanghai, China, Aug 10-13 2009.
[15] K. C. Norris, and A. H. Landzberg, “Reliability of Controlled Collapse Interconnections,” IBM Journal of Research and Development, Vol. 13, pp. 266-271, 1969.
[16] J. P. Clech, Acceleration Factors and Thermal Cycling Test Efficiency for Lead-free Sn-Ag-Cu Assemblies, SMTAI, 2005.
[17] O. Salmela, “Acceleration Factors for Lead-Free Solder Materials,” IEEE Transactions on Components and Packaging Technologies, Vol. 30, pp. 700-707, 2007.
[18] W. Dauksher, “A Second-Level SAC Solder-Joint Fatigue-Life Prediction Methodology,” IEEE Transactions on Device and Materials Reliability, Vol. 8, pp. 168-173, 2008.
[19] E. P. Busso, M. Kitano, and T. Kumazawa, “A Visco-Plastic Constitutive Model for 60/40 Tin-Lead Solder Used in IC Package Joints,” Journal of Engineering Materials and Technology, Vol. 114, pp. 331-337, 1992.
[20] K. J. Bathe, Finite Element Procedures in Engineering Analysis: Prentice Hall, 1982.
[21] S. Timoshenko, Theory of Elasticity: Mcgraw-Hill College, 1970.
[22] C. L. Dym, and I. H. Shames, Solid Mechanics: A Variational Approach, Augmented Edition: Springer, 2013.
[23] W. N. Findley, J. S. Lai, and K. Onaran, Creep and relaxation of nonlinear viscoelastic materials, with an introduction to linear viscoelasticity: Amsterdam ; New York : North-Holland Pub. Co. : sole distributors for the U.S.A. and Canada, Elsevier/North Holland, 1976.
[24] R. D. Cook, D. S. Malkus, M. E. Plesha, and R. J. Witt, Concepts and Applications of Finite Element Analysis: Wiley; 4th edition 2001.
[25] J. Chakrabarty, Theory of Plasticity: Butterworth-Heinemann; 3th edition, 2006.
[26] N. E. Dowling, Mechanical Behavior of Materials: Engineering Methods for Deformation, Fracture, and Fatigue, Upper Saddle River, New Jersey: Prentice-Hall, Inc, 1999.
[27] G. Z. Wang, Z. N. Cheng, K. Becker, and J. Wilde, “Applying Anand model to represent the Viscoplastic Deformation Behavior of Solder Alloys,” ASME Journal of Electronic Packaging, Vol. 123, pp. 247-253, 2001.
[28] Frost, and Ashby, Deformation Mechanism Maps: Pergamon Press, 1982, Chapter 2.
[29] H. Ma, and J. Suhling, “A review of mechanical properties of lead-free solders for electronic packaging,” Journal of Materials Science, Vol. 44, pp. 1141-1158, 2009.
[30] L. Anand, “Constitutive equations for hot-working of metals,” International Journal of Plasticity, Vol. 1, pp. 213-231, 1985.
[31] S. B. Brown, K. H. Kim, and L. Anand, “An internal variable constitutive model for hot working of metals,” International Journal of Plasticity, Vol. 5, pp. 95-130, 1989.
[32] F. Garofalo, Fundamentals of creep and creep-rupture in metals, New York: Macmillan Company, 1965.
[33] J. L. Chaboche, “Constitutive equations for cyclic plasticity and cyclic viscoplasticity,” International Journal of Plasticity, Vol. 5, pp. 247-302, 1989.
[34] J. L. Chaboche, “On some modifications of kinematic hardening to improve the description of ratchetting effects,” International Journal of Plasticity, Vol. 7, pp. 661-678, 1991.
[35] S. Wippler, and M. Kuna, “Experimental and numerical investigation on the reliability of leadfree solders,” Engineering Fracture Mechanics, Vol. 75, pp. 3534-3544, 2008.
[36] L. F. Coffin, “A study of the effects of cyclic thermal stress on a ductile metal,” Transactions ASME, Vol. 76, pp. 931-950, 1954.
[37] S. S. Manson, Thermal stress and low cycle fatigue, pp. 125-192, New York: McGraw-Hill, 1966.
[38] Y. Gu, and T. Nakamura, “Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages,” Microelectronics Reliability, Vol. 44, pp. 471-483, 2004.
[39] R. Darveaux, “Effect of Simulation Methodology on Solder Joint Crack Growth Correlation and Fatigue Life Prediction,” Journal of Electronic Packaging, Vol. 124, pp. 147-154, 2002.
[40] R. Darveaux, K. Banerji, A. Mawer, and G. Dody, Reliability of plastic ball grid array assembly, pp. 379-442: Chapter 13 in Ball Grid Array Tenchnology, Ed. Lau, J. H., McGraw-Hill, 1995.
[41] K. C. Wu, and K. N. Chiang, “Investigation of solder creep behavior on wafer level CSP under thermal cycling loading,” Electronics Packaging (ICEP), Toyama, Japan, April 23-25 2014.
[42] X. Chen, G. Chen, and M. Sakane, “Prediction of stress-strain relationship with an improved Anand constitutive Model For lead-free solder Sn-3.5Ag,” IEEE Transactions on Components and Packaging Technologies, Vol. 28, pp. 111-116, 2005.
[43] J. P. Clech, Review and analysis of lead-free materials properties: NIST.
[44] R. Darveaux, “Effect of simulation methodology on solder joint crack growth correlation,” Electronic Components & Technology Conference, Proceedings 50th, Las Vegas, Nevada, USA, May 21-24 2000.
[45] S. K. Kang, P. Lauro, S. Da-Yuan, D. W. Henderson, T. Gosselin, J. Bartelo, S. R. Cain, C. Goldsmith, K. J. Puttlitz, and H. Tae-Kyung, “Evaluation of thermal fatigue life and failure mechanisms of Sn-Ag-Cu solder joints with reduced Ag contents,” Electronic Components and Technology Conference, Proceedings. 54th, Las Vegas, NV, USA, June 1-4 2004.
[46] D. Xiang, P. Ning, A. Castro, J. Culler, M. Hussain, R. Lewis, and T. Michalka, “High I/O Glass Ceramic Package Pb-Free BGA Interconnect Reliability,” Electronic Components and Technology Conference, Proceedings. 55th, Lake Buena Vista, FL, May 31-June 3, 2005.
[47] R. D. Shih, S. ; Ramos, N. ; Billaut, F. ; Gopalakrishnan, L. ; Hu, M. ; Hubbard, K. ; Teng, S. ; Lee-Kim, N. ; Bezuk, S., “Reliability of HITCE Ceramic Ball Grid Array Package,” IMAPS 2005, 38th, International symposium on microelectronics, Philadelphia, Pennsylvania, USA, Sept. 25-29, 2005.
[48] N. Pan, G. A. Henshall, F. Billaut, S. Dai, M. J. Strum, R. Lewis, E. Benedetto, and J. Rayner, “An acceleration model for SnAgCu solder joint reliability under various thermal cycle conditions,” The Proceedings of the SMTA International, Chicago, IL, Sept. 25-29, 2005.