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作者(中文):楊宏德
作者(外文):Yang, Hung Te
論文名稱(中文):封裝效應於SOI電容式三軸微機電加速度計之探討
論文名稱(外文):Research on Packaging Effects of Three-axis SOI MEMS Accelerometer
指導教授(中文):江國寧
指導教授(外文):Chiang, Kuo Ning
口試委員(中文):蔡明義
趙儒民
口試委員(外文):Tsai, Ming Yi
Chao, Ru Min
學位類別:碩士
校院名稱:國立清華大學
系所名稱:動力機械工程學系
學號:102033511
出版年(民國):104
畢業學年度:103
語文別:中文
論文頁數:63
中文關鍵詞:封裝效應微機電系統加速度計共振頻率殘餘應力模態分析製程模擬有限單元應用及模擬
外文關鍵詞:Package effectSOI MEMSAccelerometerResonant frequencyResidual stressModal analysisProcess modelingFEM Applications and simulation
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近幾十年來手持裝置與微機電系統元件快速的發展,在微小化、低成本、低功耗和高精度的要求上,封裝後之微機電元件的可靠性已被提出了許多挑戰,如封裝效應產生之殘餘應力和翹曲行為等。因感測元件在製造後之共振頻率與各組織結構的勁度等性質具有不確定性,將導致其輸出性能產生不穩定性,故本研究將探討感測元件受殘餘應力影響下,其共振頻率之變化趨勢。接著將對於SOI電容式三軸微機電加速度計封裝於閘型陣列封裝之結構,進行塑封材料之固化降溫製程模擬,探討因材料間之熱膨脹係數的不同產生之封裝效應,使得感測元件因殘餘應力而產生輸出偏移之現象及其影響度。
於本研究中,利用平行板電容公式及振盪頻率原理提出一個修正電容偏差之模型,此修正模型可透過量測電容式加速度計之變化共振頻率,即可將偏移之電容差值補償至標準電容差值。由結果顯示,加速度計受到較大殘餘應力結構影響時,其引起的電容偏移量較大,加速度計之靈敏度亦明顯下降。本研究利用修正電容偏差模型,將產生偏差之電容偏移量補償至標準電容偏差量,且成功地將偏移量補償至標準量。另外,為了研究電容式加速度計之封裝溫度效應,將建立三維閘型陣列封裝模型,並嵌入電容式加速度計,並模擬環境溫度由0至300⁰C。結果發現,受溫度效應影響而產生之偏移量比受殘餘應力效應影響而產生之偏移量來得小,因此加速度計之殘餘應力效應是影響靈敏度偏移的關鍵因素之一。
In the recent years, the rapid development of handheld devices which have become smaller, cheaper, and more functionalities. However, the MEMS accelerometer after packaging has presented many challenges such as residual stress and warpage. After the sensor device processing, there were many process uncertainties may cause changes in the resonance frequency and stiffness. These uncertainties can cause the performance of MEMS sensor unstable. Furthermore, the MEMS accelerometer sensor will be embedded in the LGA packaging and simulate the shrinkage of molding compound after molding. More details of packaging effect in device will be discussed in this research.
In this research, the resonance frequency of the three-axis SOI accelerometer is successfully simulated by modal analysis, and also presents a simple compensation model for trimming the offset of capacitance differentiation using the measured resonance frequency. From the result, the accelerometer structural under high residual stress can cause the offset of capacitance differentiation. Furthermore, the sensitivities of the accelerometer are dropped significantly. By using the compensation model, the capacitance differentiation offset and the sensitivity are successfully trimmed. In addition, in order to investigate the packaging temperature effect on accelerometer structural (0-300⁰C), the LGA packaging 3D model was established. The results found that the sensitivity offsets of temperature effects are smaller than the offsets of residual stress effects, the residual stress effects will be a key factor affecting the sensitivity offsets.
目錄
摘要 I
Abstract III
目錄 V
表目錄 VIII
圖目錄 IX
第一章、 緒論 1
1.1 微機電加速度計簡介 1
1.2 研究動機 3
1.3 文獻回顧 4
1.3.1 SOI晶圓技術 4
1.3.2 沉積氧化層之殘餘應力 6
1.3.3 深反應離子蝕刻之不均勻性 9
1.3.4 封裝翹曲效應分析 11
1.4 研究目標 14
第二章、 基礎理論 16
2.1 電容式加速度計原理 16
2.1.1 梳狀電容加速度計 17
2.1.2 扭轉式電容加速度計 20
2.2 有限元素法理論 21
2.2.1 線彈性有限元素法基礎理論 22
2.2.2 材料非線性有限元素法理論 26
2.2.3 數值方法與收斂準則 30
2.3 模態分析理論 33
第三章、 研究方法 35
3.1 修正電容偏差之模型 35
3.2 電容式微機電加速度計 38
3.2.1 微機電加速度計之結構與尺寸 39
3.2.2 微機電加速度計之有限元素模型建立 40
3.2.3 微機電加速度計之邊界條件與負載設定 42
3.3 閘型陣列封裝之結構 44
3.3.1 閘型陣列封裝之結構與尺寸 44
3.3.2 閘型陣列封裝之有限元素模型建立 46
3.3.3 閘型陣列封裝之邊界條件與負載設定 47
第四章、 封裝效應模擬結果與討論 49
4.1 電容式加速度計之殘餘應力分析 49
4.1.1 初始電容式加速度計之模態分析 49
4.1.2 電容式加速度計殘餘應力效應之模擬結果 51
4.1.3 修正偏移量之結果 53
4.2 閘型陣列封裝之溫度效應分析 54
4.2.1 閘型陣列封裝之溫度效應模擬結果 55
4.2.2 修正偏移量之結果 56
第五章、 結論與未來展望 58
參考文獻 61

表目錄
表 1 1 不同寬度蝕刻後之深度與輪廓[21] 11
表 3 1 SOI晶圓各層厚度 40
表 3 2 SOI晶圓材料參數表 40
表 3 3 閘型陣列封裝各層厚度 45
表 3 4 閘型陣列封裝之材料參數 45
表 4 1 電容式加速度計之標準規格 50
表 4 2 不同殘餘應力之x方向模擬結果 52
表 4 3 不同殘餘應力之修正後模擬結果 54
表 4 4 不同溫度之x方向模擬結果 56


圖目錄
圖 1 1 電容式加速度計示意圖 2
圖 1 2 透過電容變化測量加速度之簡化電路圖[11] 3
圖 1 3 SOI晶圓結構 5
圖 1 4 氧離子植入矽晶隔離法製程 5
圖 1 5 犧牲層示意圖 7
圖 1 6 PECVD氧化層經500⁰C兩次熱循環之應力-溫度曲線[20] 7
圖 1 7 不同氧化薄膜厚度於不同溫度退火後之殘餘應力曲線[20] 8
圖 1 8 PECVD氧化層經1,100⁰C退火前後進行500⁰C熱循環實驗之 應力-溫度曲線[20] 8
圖 1 9 全晶圓蝕刻深度分佈[21] 10
圖 1 10 晶圓蝕刻深度剖面輪廓[21] 11
圖 1 11 (a)4×6基座示意圖(b)部分基座之翹曲量測[22] 13
圖 1 12 封裝Z軸位移之模擬結果[22] 13
圖 1 13 比較不同厚度封裝之翹曲情形(a)封裝厚度1.6mm之翹曲(b) 封裝厚度1.4mm之翹曲[22] 14
圖 2 1 彈簧質量阻尼系統 17
圖 2 2 梳狀電容器[11] 18
圖 2 3 扭轉式電容加速度計 21
圖 2 4 扭轉式電容加速度計之截面圖 21
圖 2 5 應力-應變曲線圖 27
圖 2 6 雙線性材料簡化模型 27
圖 2 7 等向硬化模型 29
圖 2 8 動態硬化模型 30
圖 2 9 牛頓-拉佛森增量疊代法 32
圖 3 1 面形微加工製程 38
圖 3 2 SOI電容式三軸微機電加速度計之佈局圖 39
圖 3 3 SOI電容式三軸微機電加速度計之有限元素模型 41
圖 3 4 彈簧局部放大圖 41
圖 3 5 梳狀電極局部放大圖 42
圖 3 6 Solid45元素 43
圖 3 7 微機電加速度計之邊界條件設置示意圖 43
圖 3 8 閘型陣列封裝剖面示意圖 44
圖 3 9 閘型陣列封裝有限元素模型之示意圖 46
圖 3 10 微機電加速度計嵌入封裝示意圖 47
圖 3 11 閘型陣列封裝之邊界條件設置示意圖 48
圖 4 1 初始電容式加速度計模態分析之結果(x方向) 50
圖 4 2 初始電容式加速度計模態分析之結果(y方向) 51
圖 4 3 不同殘餘應力之x方向靈敏度 53
圖 4 4 不同殘餘應力之修正後x方向靈敏度 54
圖 4 5 不同溫度之x方向靈敏度 56
圖 4 6 不同溫度修正後x方向靈敏度 57
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