帳號:guest(3.145.69.33)          離開系統
字體大小: 字級放大   字級縮小   預設字形  

詳目顯示

以作者查詢圖書館館藏以作者查詢臺灣博碩士論文系統以作者查詢全國書目
作者(中文):沈永紹
作者(外文):Shen, Yung Shao
論文名稱(中文):以摻雜氮之鈦酸鋯氧化物及鋯鉿氧化物作為電荷儲存層實現低電壓操作快閃記憶體
論文名稱(外文):Low-Voltage Operation of Flash Memory by Adopting Nitrogen-Incorporated ZrTiO4 and HfZrO as Charge Trapping Layer
指導教授(中文):巫勇賢
指導教授(外文):Wu, Yung Hsien
口試委員(中文):施君興
黃智方
口試委員(外文):Shih, Chun Hsing
Huang, Chih Fang
學位類別:碩士
校院名稱:國立清華大學
系所名稱:工程與系統科學系
學號:102011702
出版年(民國):105
畢業學年度:104
語文別:中文
論文頁數:103
中文關鍵詞:非揮發性記憶體電荷儲存層N2O氮化高介電常數介電層Orthorhombic ZrTiO4HfZrO
外文關鍵詞:Nonvolatile memoryCharge trapping layerN2O nitridationHigh-k dielectricOrthorhombic ZrTiO4HfZrO
相關次數:
  • 推薦推薦:0
  • 點閱點閱:369
  • 評分評分:*****
  • 下載下載:0
  • 收藏收藏:0
主題一實驗研究高介電常數材料ZrTiO4(k=45)在未經過及經過N2O電漿處理100秒後,做為電荷捕陷層應用於TaN/Al2O3/ZrTiO4/SiO2/Si記憶體電容元件的電荷捕陷表現。實驗發現:
1.XRD顯示,兩樣品在高溫700 oC退火後皆呈現orthorhombic的晶相性;XPS顯示,經過N2O處理者相較於未摻入氮者,其Zr 3d軌域的峰值往低鍵結能方向位移0.3 eV,此可被歸因於有些N原子的摻入取代原先O的位置,另外,N 1s軌域的XPS光譜亦可驗證N原子確實摻入ZrTiO4中並形成O-N的鍵結。
2.使用經過N2O的電漿處理的ZrTiO4作為電荷捕陷層實現快閃式記憶體有相當不錯的表現。包含在+/-7 V電壓掃描下磁滯的記憶視窗高達5.0 V、施加+7 V, 100 μs的脈衝具大的平帶電壓位移3.2 V及優異的保持性(104 s後在85 oC下電荷流失=79 %)。另外該元件的溫度相依性電流密度對電壓曲線分析,證實元件操作於普爾-法朗克機制,此被認為常發生於陷阱數目多的介電層中。這些佳化的參數歸功於使用N2O電漿處理摻入氮帶來更多且更深的陷阱能階所致。
主題二實驗研究有無氮氣通入於腔體的高介電常數材料HfZrO(k=20)做為電荷捕陷層,應用於TaN/SiO2/HfZrO/SiO2/Si記憶體電容元件的電荷捕陷表現。實驗發現:
1.XPS光譜顯示,相較於HfZrO,HfZrON的Hf 4f軌域有額外的峰值產生,此被證實為Hf-N的鍵結形成。另外,N 1s軌域的XPS光譜亦可驗證Hf-N鍵結發生。
2.使用HfZrON作為電荷捕陷層強化了HfZrO在記憶體的電性表現。包含+/-10 V電壓掃描下磁滯記憶視窗由2.7 V提升至5.0 V、施加+10 V,1 ms的脈衝具更大的平帶電壓位移2.6 V,同時也具有優異的保持性(104 s後在85 oC下電荷流失=86 %)。另外,該元件溫度相依性的電流密度對電壓曲線證實元件操作於躍遷機制,此被認為發生於缺陷密度高的薄膜。此優化特性歸因於同腔體通入氮氣帶來更多且更深的陷阱能階。
From the experiment of topic 1, the charge trapping characteristics were investigated by using high-k ZrTiO4(k=45) with and without N2O plasma treatment for 100 sec as charge trapping layer based on the TaN/Al2O3/ZrTiO4/SiO2/Si (MONOS) capacitors.
1. By XRD spectroscopy, both samples exhibit orthorhombic phase after 700 oC high temperature annealing. From XPS analysis, the N2O treated ZrTiO4 presents the peaks shift to lower binding energy by 0.3 eV than untreated one, which should be mainly due to the occurrence of few replacements of O by N, as the Zr-O bond is stronger than Zr-N bond. Moreover, the presence of O-N compound can be further confirmed by the N 1s spectrum.
2.The ZrTiO4 after N2O treatment as charge trapping layer displayed promising performance in terms of a large hysteresis window (5 V) by +-/7 V sweeping voltage, large flat band voltage (VFB) shift (3.2 V) at a low gate voltage of +7 V for 100 μs, a low charge loss=79 % after 104 sec even at 85 oC. Based on the temperature dependent current density versus electric field measurement, the dominate conduction mechanisms in N2O treated ZrTiO4 film is Poole-Frenkel emission which is also confirmed high density of traps in the film. These advantages can be associated with higher trap density and generated deep-level traps due to nitrogen incorporation by N2O plasma.
From the experiment of topic 2, charge trapping characteristics of HfZrO(k=20) with and without in-situ nitrogen incorporation were investigated based on the TaN/SiO2/HfZrO/SiO2/Si (MONOS) capacitors.
1. Compared with the HfZrO film, the additional peak of Hf 4f spectrum for the HfZrON can be observed due to the formation of Hf-N compound. Moreover, the presence of Hf-N compound can be further confirmed by the N 1s spectrum.
2. The HfZrON as charge trapping layer displayed promising performance than using HfZrO in terms of larger hysteresis window (3.8 V) by +-/10 V sweeping voltage, larger flat band voltage (VFB) shift (2.6 V) at a low gate voltage of +10 V for 1 ms, a lower charge loss=86 % after 104 sec even at 85 oC. Based on the temperature dependent current density versus electric field measurement, the dominate conduction mechanisms in HfZrO and HfZrON film are hopping conduction which is also confirmed high density of traps in the film. These advantages can be associated with higher trap density and generated deep-level traps due to nitrogen incorporation by introduced nitrogen in-situ deposition.
摘要..................................................i
Abstract.............................................ii
致謝.................................................iv
總目錄................................................v
圖目錄...............................................viii
表目錄...............................................xiii

第一章 緒論.............................................1
1-1 研究背景............................................1
1-2 研究動機............................................3
1-2-1 【主題一】實驗研究動機..............................3
1-2-2 【主題二】實驗研究動機..............................5
1-3 文獻回顧…............................................6
1-3-1 新型高介電常數材料作為電荷捕陷層應用於非揮發性記憶體之研究.....................................................6
1-3-2 透過氮摻入於高介電常數材料增強其捕陷能力之研究........10

第二章 快閃記憶體原理與操作..............................20
2-1 快閃式記憶體元件結構.................................20
2-2 磁滯曲線的順逆時針操作與記憶視窗大小...................21
2-3 頻率相依性的電容-電壓曲線及電導-電壓曲線...............22
2-4 寫入及抹除速度與機制討論..............................23
2-4-1 寫入操作..........................................24
2-4-2 抹除操作..........................................25
2-5 資料耐久性..........................................26
2-6 資料保持性..........................................26

第三章 實驗規劃與製程流程................................31
3-1【主題一】 TaN/SiO2/N2O:ZrTiO4/SiO2/Si元件製程流程.....................................................32
3-2【主題二】 TaN/SiO2/HfZrON/SiO2/Si元件製程流程.....................................................34

第四章 實驗結果與討論....................................43
4-1【主題一】以N2O電漿處理結晶態ZrTiO4作為電荷捕陷層應用於低電壓操作的非揮發性記憶體......................................43
4-1-1 X光繞射儀........................................43
4-1-2 X光光電子能譜儀...................................44
4-1-3 電容-電壓曲線與記憶視窗............................46
4-1-4 儲存陷阱密度......................................47
4-1-5 頻率相依性的電容-電壓曲線及電導-電壓曲線.............47
4-1-6 電流密度-電壓曲線..................................48
4-1-7 溫度相依性的電流密度-電壓曲線.......................49
4-1-8 普爾-法蘭克散射機制................................49
4-1-9 寫入/抹除速度.....................................49
4-1-10 耐久性..........................................50
4-1-11 保持性...........................................51
4-2【主題二】氮摻入結晶態HfZrO作為電荷捕陷層應用於低電壓操作的非揮發性記憶體..............................................52
4-2-1 X光光電子能譜儀...................................52
4-2-2 電容-電壓曲線與記憶視窗............................53
4-2-3 儲存陷阱密度......................................54
4-2-4 頻率相依性的電容-電壓曲線及電導-電壓曲線.............54
4-2-5 電流密度-電壓曲線.................................55
4-2-6 溫度相依性的電流密度-電壓曲線......................56
4-2-7 躍遷機制.........................................56
4-2-8 寫入/抹除速度.....................................57
4-2-9 耐久性...........................................58
4-2-10 保持性..........................................58

第五章 結論與未來展望....................................82

參考文獻................................................83
[1] M. She, T. J. King, C. Hu, W. Zhu, Z. Luo, J. P. Han, and T. P. Ma, “JVD Silicon Nitride as Tunnel Dielectric in P-Channel Flash Memory,” IEEE Electron Device Lett., vol. 23, pp. 91–93, 2002.
[2] C. Zhao, C. Z. Zhao, S. Taylor, and P. R. Chalker, “Review on Non-Volatile Memory with High-K Dielectrics: Flash For Generation beyond 32 nm,” Mater., vol. 7, pp. 5117–5145, 2014.
[3] R. Waser and M. Aono, “Nanoionics-Based Resistive Switching Memories.,” Nat. Mater., vol. 6, pp. 833–40, 2007.
[4] T. Kim, Y. K. Kim, and W. Park, “Technological Issues for High-Density MRAM Development,” J. Magn. Magn. Mater., vol. 282, pp. 232–236, 2004.
[5] Y. Shimada, “FeRAM: Next Generation Challenges and Future Directions,” in Proc. IEEE Int. Symp. Appl. Ferroelectr., p. 4, 2007.
[6] R. Zhao, L. P. Shi, W. J. Wang, H. X. Yang, H. K. Lee, K. G. Lim, E. G. Yeo, and E. K. Chua, “Study of Phase Change Random Access Memory (PCRAM) at the Nano-Scale,” in Proc. Non-Volatile Memory Technology Symp.(NVMTS), pp. 36–39, 2007.
[7] Y. Chang, Y. Chang, T. Kuo, Y. Li, and H. Li, “Achieving SLC Performance with MLC Flash Memory,” in Proc. of ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 3–8, 2015.
[8] Y. Yamauchi, Y. Kamakura, and T. Matsuoka, “Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory,” IEEE Trans. Electron Devices, vol. 60, pp. 2518–2524, 2013.
[9] H. Pon, “Technology Scaling Impact on NOR and NAND Flash Memories and Their Applications,” in Proc. 8th Int. Conf. Solid-State Integr. Circuit Technol., pp. 697–700, 2007.
[10] C. Y. Lu, K. Y. Hsieh, and R. Liu, “Future Challenges of Flash Memory Technologies,” Microelectron. Eng., vol. 86, pp. 283–286, 2009.
[11] G. Zhang, X. P. Wang, W. J. Yoo, and M. F. Li, “Spatial Distribution of Charge Traps in a SONOS-Type Flash Memory Using a High-K Trapping Layer,” IEEE Trans. Electron Devices, vol. 54, pp. 3317–3324, 2007.
[12] C. Sun, L. Liu, Z. Zhang, and L. Pan, “Comparison of Reliability of Single and Stacked high-k Structures of Charge Trapping Memories,” IEEE Int. Integr. Reliab.Workshop Final Report.(IRW), pp. 59–61, 2013.
[13] S. Jeon, J. H. Han, J. Lee, C. J. Choi, S. Choi, H. Hwang, and C. Kim, “High Work-Function Metal Gate and High-K Dielectrics for Charge Trap Flash Memory Device Applications,” in Proc. ESSDERC, pp. 5–8, 2005.
[14] A. A. Lavrentyev, B. V. Gabrelian, P. N. Shkumat, I. Y. Nikiforov, T. N. Bondarenko, E. I. Kopylova, O. Y. Khyzhun, M. V. Karpets, and J. J. Rehr, “Electronic Structure of ZrTiO4 and HfTiO4: Self-Consistent Cluster Calculations and X-Ray Spectroscopy Studies,” J. Phys. Chem. Solids, vol. 72, pp. 83–89, 2011.
[15] Y. H. Wu, R. J. Lyu, M. L. Wu, L. L. Chen, and C. C. Lin, “Integration of Amorphous Yb2O3 and Crystalline ZrTiO4 as Gate Stack for Aggressively Scaled MOS Devices,” IEEE Electron Device Lett., vol. 33, pp. 426–428, 2012.
[16] C. Y. Wu, C. H. Hsieh, C. W. Lee, and Y. H. Wu, “Crystalline ZrTiO4 Gated P-Metal-Oxide-Semiconductor Field Effect Transistors with Sub-nm Equivalent Oxide Thickness Featuring Good Electrical Characteristics and Reliability,” Appl. Phys. Lett., vol. 106, pp. 3–7, 2015.
[17] J. H. Park, S. Member, G. S. Jang, H. Y. Kim, S. K. Lee, and S. K. Joo, “High-Performance Poly-Si Thin-Film Transistor with High-K ZrTiO4 Gate Dielectric,” IEEE Electron Device Lett., vol. 36, pp. 920–922, 2015.
[18] D. Kim, D. Park, G. Kim, and S. Choi, “Dielectric Properties of ZrTiO4 Thin Films Synthesized by Sol-Gel Method,” Met. Mater. Int., vol. 10, pp. 361–362, 2004.
[19] M. Viticoli, G. Padeletti, S. Kaciulis, G. M. Ingo, L. Pandolfi, and C. Zaldo, “Structural and Dielectric Properties of ZrTiO4 and Zr0.8Sn0.2TiO4 Deposited by Pulsed Laser Deposition,” Mater. Sci. Eng. B, vol. 118, pp. 87–91, 2005.
[20] H. Dutta and S. K. Pradhan, “In-Situ High Temperature Annealing of Nanostructured ZrTiO4 Prepared by Mechanical Alloying,” Phys. E: Low-Dimensional Syst. Nanostructures, vol. 42, pp. 1772–1776, 2010.
[21] G. Lucovsky, Y. Zhang, J. L. Whitten, D. G. Schlom, and J. L. Freeouf, “Separate and Independent Control of Interfacial Band Alignments and Dielectric Constants in Transition Metal Rare Earth Complex Oxides,” Microelectron. Eng., vol. 72, pp. 288–293, 2004.
[22] J. Robertson, “High Dielectric Constant Oxides,” Eur. Phys. J. Appl. Phys., vol. 28, pp. 265–291, 2004.
[23] T. S. Boscke, P. Y. Hung, P. D. Kirsch, M. A. Quevedo-Lopez, and R. Ramirez-Bon, “Increasing Permittivity in HfZrO Thin Films by Surface Manipulation,” Appl. Phys. Lett., vol. 95, p. 052904, 2009.
[24] D. Tahir, E. K. Lee, S. K. Oh, T. T. Tham, H. J. Kang, H. Jin, S. Heo, J. C. Park, J. G. Chung, and J. C. Lee, “Band Alignment of Atomic Layer Deposited (ZrO2)x(SiO2)1−x Gate Dielectrics on Si (100),” Appl. Phys. Lett., vol. 94, p. 212902, 2009.
[25] S. Maikap, H. Y. Lee, T. Y. Wang, P. J. Tzeng, C. C. Wang, L. S. Lee, K. C. Liu, J. R. Yang, and M. J. Tsai, “Charge Trapping Characteristics of Atomic-Layer-Deposited HfO2 Films with Al2O3 as a Blocking Oxide for High-Density Non-Volatile Memory Device Applications,” Semicond. Sci. Technol., vol. 22, pp. 884–889, 2007.
[26] Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, “A MONOS-Type Flash Memory Using a High-K HfAlO Charge Trapping Layer,” Electrochem. Solid-State Lett., vol. 7, p. G198, 2004.
[27] G. Congedo, A. Lamperti, L. Lamagna, and S. Spiga, “Stack Engineering of TANOS Charge-Trap Flash Memory Cell Using High-K ZrO2 Grown by ALD as Charge Trapping Layer,” Microelectron. Eng., vol. 88, pp. 1174–1177, 2011.
[28] T. M. Pan and T. Y. Yu, “Comparison of the Structural Properties and Electrical Characteristics of Pr2O3, Nd2O3 and Er2O3 Charge Trapping Layer Memories,” Semicond. Sci. Technol., vol. 24, p. 095022, 2009.
[29] L. F. Liu, L. Y. Pan, Z. G. Zhang, and J. Xu, “Impact of Band-Engineering to Performance of High-K Multilayer Based Charge Trapping Memory,” Chinese Phys. Lett., vol. 32, p. 088501, 2015.
[30] X. D. Huang, J. K. O. Sin, and P. T. Lai, “BaTiO3 as Charge-Trapping Layer for Nonvolatile Memory Applications,” Solid. State. Electron., vol. 79, pp. 285–289, 2013.
[31] W. S. Kim, D. W. Kwak, J. S. Oh, D. W. Lee, and H. Y. Cho., “The Origin of Trap and Effect of Nitrogen Plasma in the Oxide-Nitride-Oxide Structures for Non-Volatile Memory,” J. Korean Phys. Soc., vol. 57, pp. 255-259, 2010.
[32] X. D. Huang, P. T. Lai, L. Liu, and J. P. Xu, “Nitrided SrTiO3 as Charge-Trapping Layer for Nonvolatile Memory Applications,” Appl. Phys. Lett., vol. 98, p. 242905, 2011.
[33] Q. B. Tao and P. T. Lai, “Nitrided GdTiO as Charge-Trapping Layer for Flash Memory Applications,” in Proc. 11th Int. Conf. Solid-State Integr. Circuit Technol., pp. 5–7, 2012.
[34] X. D. Huang, J. Sin, and P. T. Lai, “Nitrided La2O3 as Charge-Trapping Layer for Nonvolatile Memory Applications,” Appl. Phys. Lett., vol. 12, pp. 306–310, 2012.
[35] J. C. J. Xu and L. Liu, “Performance Improvements of Metal-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory with ZrO2 Charge-Trapping Layer by Using Nitrogen Incorporation,” Appl. Phys. Express, vol. 6, p. 084202, 2013.
[36] Y. Wu, L. Chen, J. Wu, M. Wu, C. Lin, and C. Chang, “Nonvolatile Memory with Nitrogen-Stabilized Cubic-Phase ZrO2 as Charge-Trapping Layer,” IEEE Electron Device Lett., vol. 31, pp. 1008–1010, 2010.
[37] S. S. Gong, M. E. Burnham, N. D. Theodore, and D. K. Schroder, “Evaluation of Qbd for Electrons Tunneling from the Si/SiO2 Interface Compared to Electron Tunneling from the Poly-Si/SiO2 Interface,” IEEE Trans. Electron Devices, vol. 40, pp. 1251–1257, 1993.
[38] B. S. Sahu, F. Gloux, A. Slaoui, M. Carrada, D. Muller, J. Groenen, C. Bonafos, and S. Lhostis, “Effect of Ion Implantation Energy for the Synthesis of Ge Nanocrystals in SiN Films with HfO2/SiO2 Stack Tunnel Dielectrics for Memory Application.,” Nanoscale Res. Lett., vol. 6, p. 177, 2011.
[39] N. Konofaos and E. K. Evangelou, “Electrical Characterization of the SiON/Si Interface for Applications on Optical and MOS Devices,” Semicond. Sci. Technol., vol. 18, pp. 56–59, 2002.
[40] S. Huang, S. Banerjee, and S. Oda, “C-V and G-V Measurements Showing Single Electron Trapping in Nanocrystalline Silicon Dot Embedded in MOS Memory Structure,” in Proc. Mat. Res. Soc. Symp.., vol. 686, p. A8.8.1, 2002.
[41] J. Lu, Y. Kuo, J. Yan, and C. H. Lin, “Nanocrystalline Silicon Embedded Zirconium-Doped Hafnium Oxide High-K Memory Device,” Jpn. J. Appl. Phys 2, vol. 45, pp. 8–11, 2006.
[42] A. Ali, H. Madan, S. Koveshnikov, and S. Datta, “Small Signal Response of Inversion Layers in High Mobility In0.53Ga0.47As MOSFETs Made with Thin High-k Dielectrics,” ECS Trans. , vol. 25, pp. 271–284, 2009.
[43] J. Son, V. Chobpattana, B. M. McSkimming, and S. Stemmer, “In-Situ Nitrogen Plasma Passivation of Al2O3/GaN Interface States,” J. Vac. Sci. Technol. A, vol. 33, p. 020602, 2015.
[44] Y. H. Wu, L. L. Chen, Y. S. Lin, M. Y. Li, and H. C. Wu, “Nitrided Tetragonal ZrO2 as the Charge-Trapping Layer for Nonvolatile Memory Application,” IEEE Electron Device Lett., vol. 30, pp. 1290–1292, 2009.
[45] C. E. Sun, C. Y. Chen, K. L. Chu, Y. S. Shen, C. C. Lin, and Y. H. Wu, “ZnO/NiO Diode-Based Charge-Trapping Layer for Flash Memory Featuring Low-Voltage Operation,” ACS Appl. Mater. Interfaces, vol. 7, pp. 6383–6390, 2015.
[46] C. Yeh and C. Chen, “Controlling Fluorine Concentration and Thermal Annealing Effect on Liquid-Phase Deposited SiO2-xFx Films,” J. Electrochem. Soc., vol. 142, pp. 3579–3583, 1995.
[47] P. Kringhoj and A. Larsen, “Anomalous Diffusion of Tin in Silicon,” Phys. Rev. B, vol. 56, pp. 6396–6399, 1997.
[48] K. M. Chang, C. H. Lai, C. F. Chen, P. S. Kuo, Y. M. Chen, T. Y. Chang, A. J. W. Whang, Y. L. Lai, H. Y. Chen, and I. J. Hsieh, “Self-Passivation by Fluorine Plasma Treatment and Low-Temperature Annealing in SiGe Nanowires for Biochemical Sensors,” J. Nanosci., vol. 2014, p. 7, 2014.
[49] M. Specht, H. Reisinger, F. Hofmann, T. Schulz, E. Landgraf, R. J. Luyken, W. Rosner, M. Grieb, and L. Risch, “Charge Trapping Memory Structures with Al2O3 Trapping Dielectric for High-Temperature Applications,” Solid. State. Electron., vol. 49, pp. 716–720, 2005.
[50] M. Specht, H. Reisinger, M. Stadele, F. Hofmann, A. Gschwandtner, E. Landgraf, R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, W. Rosner, J. Kretz, and L. Risch, “Retention Time of Novel Charge Trapping Memories Using Al2O3 Dielectrics,” in Proc. Eur. Solid-State Device Res. Conf., pp. 155–158, 2003.
[51] B. Sen, H. Wong, B. L. Yang, A. P. Huang, P. K. Chu, V. Filip, and C. K. Sarkar, “Nitrogen Incorporation into Hafnium Oxide Films by Plasma Immersion Ion Implantation,” Jpn. J. Appl. Phys., vol. 46, pp. 3234–3238, 2007.
(此全文未開放授權)
電子全文
摘要
 
 
 
 
第一頁 上一頁 下一頁 最後一頁 top
* *