隨著元件的微縮，短通道效應、製程技術以及物理極限將是一般傳統電晶體將會面臨的挑戰。無接面電晶體是一種未來可解決這些困難的新穎元件，無接面電晶體的特點就是其源極、汲極以及通道摻雜型態以及濃度皆相同。因此此電晶體除了可以減少製程步驟、降低熱預算之外，還能降低短通道效應。但無接面電晶體必須將元件主動層做得夠薄才能使通道完全空乏，得到較佳的開關特性及較低的漏電流。
為了克服無接面電晶體的缺點，我們提出使用乾式蝕刻的方式對多晶矽通道進行薄化，形成溝槽式的超薄主動層。相較於傳統直接沉積超薄多晶矽主動層的方式，乾式蝕刻薄化方式可以得到較大的晶粒與較少的晶界。在形成超薄溝槽式主動層時，抬升式源汲極結構也同時完成。再搭配上環繞式閘極增加閘極控制能力，提升元件開關能力以及降低漏電流。
在此篇的研究中，我們提出環繞式閘極與超薄主動層(0.65nm) P 型無接面多晶電晶體的的研究。在此研究中我們使用低溫多晶矽製程與乾式蝕刻製程成功製造出擁有超薄主動層(0.65nm)的P型無接面多晶矽電晶體。此元件展現出極佳的電性，像是SS達到接近理想值的 60mV/dec以及極佳的開關特性，這主要是因為元件夠薄使得閘極擁有很好的控制能力。由於溝槽式主動層同時也形成抬升式源汲極結構的緣故，此元件有相當不錯的電流開關比 (ION/IOFF=109)。在短通道效應的抑制上也展現出極佳的能力，其DIBL值為0.4mV/V。
此篇研究中分為是元件製程、基礎元件特性分析、模擬物性分析以及高溫分析。在模擬方面，我們使用了Sentaurus TCAD 軟體模擬此元件的物性以及電性，從模擬物性分析中發現能帶穿隧效應發生在此元件，以至於此元件能獲得非常良好的開關特性。

As the feature size of logic device has been scaled continuously, conventional inversion-mode Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) face a lot of challenges such as random dopant fluctuation, physical limitation and short channel effect (SCE). Junctionless FET is the one solution key in the future devices. JL-FET is a novel device, which has heavily doping channel with the same type to that of source and drain. Therefore, JL-FET has a nearly negligible drain-induced barrier lowering (DIBL) , a slight short channel effect (SCE) and less thermal budget in process of fabrication. Because of the high concentration of dopants in channel, using a fully-depleted to turn off JL-FET is necessary. Ultra-thin body (UTB) have been employed to solve those problems.
In this work, we adopt reactive ion etch (RIE) to form the polycrystalline silicon (poly-Si) UTB instead of directly depositing the thin-film as the poly-Si in JL-FET. The RIE thinning process could get larger grain size and less grain boundary than directly depositing the thin-film. After RIE thinning process, the nanowires look like the trench structure and the raise S/D structure is completed at the same time. In addition, gate-all-around (GAA) structure combine with UTB could improve gate control ability, that improve sub-threshold swing (SS) and reduce OFF-state leakage current.
This work is the first time to demonstrate the GAA p-channel JL poly-Si transistor with 0.65-nm ultra-thin body. Using low temperature poly-Si to fabricate GAA trench JL-FET with ultra-thin body are successfully fabricated. The sub-threshold swing (SS) of GAA trench JL-FET is 60mV/decade, and the ON/OFF current ratio exceeds 109 because of the excellent gate control ability, ultra-thin body and raise S/D structure. The GAA trench JL-FET has a negligible DIBL value of 0.4mV/V, indicating great suppression of the short channel effect.
Firstly, this work focuses on the device process, basic device characteristics analysis, device simulation and temperature performance. In simulation, we use Sentaurus TCAD to analyze the physical and electrical results. And the band-to-band tunneling (BTBT) will take place at the channel/drain junction region. This mechanism result in the GAA trench JL-FET with low SS.

中文摘要......................................................................................................................................i
Abstract......................................................................................................................................iii
Acknowledge..............................................................................................................................v
Contents.....................................................................................................................................vi
Table Captions vii
Figure Captions viii
Chapter 1.................................................................................................................................- 1 -
Introduction.............................................................................................................................- 1 -
1-1 Challenge of Scaling Down the Device - 1 -
1-2 Introduction of Junctionless Device - 3 -
1-3 Motivation - 12 -
1-4 Thesis Organization - 16 -
Chapter 2...............................................................................................................................- 17 -
Junctionless Mechanism - 17 -
2-1 Basic Principle of Junctionless Transistor - 17 -
2-2 Short Channel Effect (SCE) in Junctionless transistor - 23 -
2-3 Threshold voltage in junctionless transistor - 25 -
2-4 Quantum Confinement Effect in TFT with Ultra-Thin Body - 27 -
Chapter 3...............................................................................................................................- 29 -
Device Fabrication and Structure - 29 -
3-1 Device Fabrication Process - 29 -
3-2-1 SEM and AFM image of device structure - 31 -
3-2-2 TEM image of device structure - 35 -
Chapter 4...............................................................................................................................- 37 -
Characteristics Analysis - 37 -
4-1-1 Characteristics Analysis for GAA and Planar device - 37 -
4-1-2 Characteristics Analysis for Trench and W/O Trench - 45 -
4-2 Quantum Confinement Effect in Threshold Voltage - 47 -
4-3 Device Simulation - 49 -
4-4 Device Temperature Performance - 52 -
Chapter 5............................................................................................................................... - 56 -
Conclusion............................................................................................................................- 56 -
Reference..............................................................................................................................- 58 -

中文摘要......................................................................................................................................i
Abstract......................................................................................................................................iii
Acknowledge..............................................................................................................................v
Contents.....................................................................................................................................vi
Table Captions vii
Figure Captions viii
Chapter 1.................................................................................................................................- 1 -
Introduction.............................................................................................................................- 1 -
1-1 Challenge of Scaling Down the Device - 1 -
1-2 Introduction of Junctionless Device - 3 -
1-3 Motivation - 12 -
1-4 Thesis Organization - 16 -
Chapter 2...............................................................................................................................- 17 -
Junctionless Mechanism - 17 -
2-1 Basic Principle of Junctionless Transistor - 17 -
2-2 Short Channel Effect (SCE) in Junctionless transistor - 23 -
2-3 Threshold voltage in junctionless transistor - 25 -
2-4 Quantum Confinement Effect in TFT with Ultra-Thin Body - 27 -
Chapter 3...............................................................................................................................- 29 -
Device Fabrication and Structure - 29 -
3-1 Device Fabrication Process - 29 -
3-2-1 SEM and AFM image of device structure - 31 -
3-2-2 TEM image of device structure - 35 -
Chapter 4...............................................................................................................................- 37 -
Characteristics Analysis - 37 -
4-1-1 Characteristics Analysis for GAA and Planar device - 37 -
4-1-2 Characteristics Analysis for Trench and W/O Trench - 45 -
4-2 Quantum Confinement Effect in Threshold Voltage - 47 -
4-3 Device Simulation - 49 -
4-4 Device Temperature Performance - 52 -
Chapter 5............................................................................................................................... - 56 -
Conclusion............................................................................................................................- 56 -
Reference..............................................................................................................................- 58 -

Chapter 1

1-1. G. E. Moore, “Cramming more components onto integrated circuits”, Proceedings of the IEEE, vol. 86, pp. 82-85, 1965
1-2. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
1-3. Horng-Chih Lin, Cheng-I Lin, Zer-Ming Lin, Bo-Shiuan Shie, and Tiao-Yuan Huang, “Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 60, NO. 3, MARCH 2013
1-4. H. T. Lue, T. H. Hsu, Y. H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S. Y. Wang, J. Y. Hsieh, L. W. Yang, T. Yang, K. C. Chen, K. Y. Hsieh, and C. Y. Lu, “A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device,” in VLSI Symp. Tech. Dig., pp. 131–132, 2010.
1-5. Bio KIM, Seung-Hyun LIM, Dong Woo KIM, Toshiro NAKANISHI, Sangryol YANG, Jae-Young AHN, Han Mei CHOI, Kihyun HWANG, Yongsun KO, Chang-Jin KANG, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, Reliability Physics Symposium (IRPS), IEEE International,., pp. 126-129, 2011.
1-6. Hung-Bin Chen, Yung-Chun Wu, Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope,” in VLSI Symp. Tech. Dig., pp. 232-233, 2013
1-7. Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota, “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm),” Electron Devices Meeting (IEDM), 2012 IEEE International, 2012.
1-8. Chi-Woo Lee, Adrien Borne, Isabelle Ferain, Aryan Afzalian, Member, IEEE, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, Jean-Pierre Colinge, “High-Temperature Performance of Silicon Junctionless MOSFETs”, ED, vol. 57, pp. 620 – 624, 2010.
1-9. Mu-Shih Yeh, Yung-Chun Wu, Min-Hsin Wu, Yi-Ruei Jhan, Ming-Hsien Chung, and Min-Feng Hung, “High Performance Ultra-Thin Body (2.4nm) Poly-Si Junctionless Thin Film Transistors with a Trench Structure”, Electron Devices Meeting (IEDM), 2014 IEEE International, 2014.
1-10. J.P Colinge, “Multiple-gate SOI MOSFETs,” Solid-State Electronics 48, 2004, 897–905
1-11. J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications, Springer, Verlag Berlin Heidelberg, pp. 187–200, 2011.

Chapter 2

2-1. J.P. Colinge, Semiconductor-On-Insulator Materials for NanoElectronics Applications, chapter 10, pp.187, 2011.
2-2. C.W. Lee, I. Ferain, A. Kranti, N. Dehdashti Akhavan, P. Razavi, R. Yan, R. Yu, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, S. Gheorghe, R. Murphy, J.P. Colinge, “Short-Channel Junctionless Nanowire Transistors,” 2010, solid state devices and materials (SSDM)
2-3. P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J. Colinge, “Influence of channel material properties on performance of nanowire transistors,” J. Appl. Phys., vol. 111, no. 12, pp. 124509-1–124509-8, Jun. 2012.
2-4. R. Trevisoli, R. Doria, M. de -Souza, and M. Pavanello, “Threshold voltage in junctionless nanowire transistors,” Semicond. Sci. Technol., vol. 26, p. 105 009, Oct. 2011.
2-5. Xiaojun Guo, Tomoyuki Ishii, and S. R. P. Silva, “Improving Switching Performance of Thin-Film Transistors in Disordered Silicon,” EDL, 2008, vol. 29, pp. 588–591.

Chapter 4

4-1. J. P. Colinge, “Nanowire Junctionless Transistors,” Tyndall National Institute University College Cork, 2010.
4-2. J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications, Springer, Verlag Berlin Heidelberg, pp. 187–200, 2011.
4-3. R. Trevisoli, R. Doria, M. de -Souza, and M. Pavanello, “Threshold voltage in junctionless nanowire transistors,” Semicond. Sci. Technol., vol. 26, p. 105 009, Oct. 2011.
4-4. TCAD Sentaurus Device, Ver.G-2012.06, Synopsys 2012.
4-5. Chi-Woo Lee, Adrien Borne, Isabelle Ferain, Aryan Afzalian, Member, IEEE, Ran Yan, Nima Dehdashti Akhavan, Pedram Razavi, and Jean-Pierre Colinge, “High-Temperature Performance of Silicon Junctionless MOSFETs”, ED, vol. 57, pp. 620 – 624, 2010.
4-6. Xiaojun Guo, Tomoyuki Ishii, and S. R. P. Silva, “Improving Switching Performance of Thin-Film Transistors in Disordered Silicon,” EDL, 2008, vol. 29, pp. 588–591.
Chapter 5

5-1. Bio KIM, Seung-Hyun LIM, Dong Woo KIM, Toshiro NAKANISHI, Sangryol YANG, Jae-Young AHN, Han Mei CHOI, Kihyun HWANG, Yongsun KO, Chang-Jin KANG, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash”, Reliability Physics Symposium (IRPS), IEEE International,., pp. 126-129, 2011.
5-2. Hung-Bin Chen1, Yung-Chun Wu, Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng, “Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope,” in VLSI Symp. Tech. Dig., pp. 232-233, 2013
5-3. Shinji Migita, Yukinori Morita, Meishoku Masahara, and Hiroyuki Ota, “Electrical Performances of Junctionless-FETs at the Scaling Limit (LCH = 3 nm),” Electron Devices Meeting (IEDM), 2012 IEEE International, 2012,
5-4. Xiao jun Guo, Tomoyuki Ishii, and S. R. P. Silva, “Improving Switching Performance of Thin-Film Transistors in Disordered Silicon,” EDL, 2008, vol. 29, pp. 588–591.