隨著大數據時代的來臨，對於非揮發性記憶體需求的日益激增。因此，元件除了高儲存密度，同時保有高效能以及優良可靠度特性的元件是有其必要的。為了改善元件的操作特性與效能，高鍺濃度及矽化鍺通道被視為是最有潛力的一種提升效能的方式，並且可同時維持元件的微縮能力。在本論文中，主要將探討鍺成長於複晶矽奈米線通道，應用在快閃記憶體元件對其電性上的表現加以探討。
第一個實驗將鍺成長在複晶矽電荷反轉式快閃記憶體元件的奈米線通道上。本實驗中，將比較鍺與矽覆蓋層成長、矽化鍺與矽覆蓋層成長以及無成長的元件進行比較。具鍺成長的元件不論在寫入或抹除速度上都是表現最優異的; 在電荷保持力特性上表現差異並不明顯; 在元件耐久力上具成長的元件表現較佳，因為較快的寫抹速度降低了對於穿隧氧化層的損害。
第二個實驗將低溫沉積二氧化鉿/氮化矽堆疊電荷捕捉層應用在鍺成長於奈米線通道上的元件結構中。氮化矽薄膜是藉由感應耦合電漿化學氣相沉積系統沉積。降低含鍺成分的元件在製程熱預算的考量，並同時可以保有寫抹速度的提升、元件耐久力較佳等優勢，具二氧化鉿/氮化矽堆疊結構可提升元件在電荷保持力的特性。
第三個實驗將延續第二個實驗的介電層結構，將鍺成長於複晶矽無接面快閃記憶體元件的奈米線通道上。實驗中將比較具有鍺與矽覆蓋層成長的元件及無成長的元件。不論應用在電荷反轉式及無接面元件，具成長元件在寫抹速度、耐久度皆有所提升; 電荷保持力特性表現上可以與無成長元件擁有相互匹配的表現。

With the recent development of Big Data, the demand of nonvolatile memory increases rapidly. Therefore, nonvolatile memory devices of high storage density with high performance and reliability are necessary. In order to improve the efficiency, high- concentration germanium buried channel is considered as a promising way to enhance the performance, while preserving the scaling-down ability. This thesis proposes an implementation of Ge buried channel on the surface of poly silicon nanowire channels and investigates its electrical characteristics. Three experiments are carried out to test the performance of flash memory devices with the proposed the IM and JL mode components.
In the first experiment, germanium is grown on nanowire channel of inversion mode flash memory device. Three different conditions are compared: 1) the growth of Ge and silicon cap-layer, 2) the growth of SiGe and silicon cap-layer, and 3) devices without any growth. Results show that devices with Ge growth have the fast programming and erasing speed. No obvious differences of retention characteristics were seen among the three conditions. The devices with epitaxial growth (condition 1 & 2) exhibit better endurance characteristics because their faster P/E speed reduces the damage of tunneling layer.
The second experiment studies low temperature formed HfO2/SiNx stacked trapping layer on three channel structures described in the first experiment. The nitride thin film was deposited by inductively coupled plasma chemical vapor deposition at 450 ℃ in order to reduce thermal cycles in fabrication processes of the devices with Ge containing, which achieves the enhancement of P/E speed and endurance. Results of the second experiment show that the low temperature formed HfO2/SiNx stacked trapping layer can further improve the retention characteristics as compared to results in the first experiment.
The third experiment investigates junctionless nanowire flash memory devices with stacked trapping layer in the second experiment. The junctionless devices with Ge buried channel and those without ones are compared. Results show that whatever modes (JL / IM) they are, the program, erase speed and endurance performance can be effectively improved by buried channel. The retention characteristics of devices with buried channels can be still similar as compared to those without ones.

摘要 I
Abstract II
致謝 IV
目錄 V
圖目錄 VIII
表目錄 XIII
第 1 章 序論 1
1.1 快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體元件 1
1.1.2 電荷捕陷式快閃記憶體元件 2
1.2 多晶矽薄膜電晶體 3
1.3 多向式閘極結構與奈米線通道式快閃記憶體元件 4
1.4 高介電係數材料與能帶工程之介紹 5
1.4.1 高介電係數材料 5
1.4.2 能帶工程 6
1.5 無接面快閃記憶體元件介紹 7
1.6 鍺與矽化鍺掩埋式通道之應用 9
1.7 各章摘要 10
第 2 章 快閃記憶體元件的製程與操作方法 17
2.1 奈米線通道快閃記憶體元件製程 17
2.1.1 傳統反轉層元件 17
2.1.2 無接面元件 18
2.2 快閃記憶體元件寫入與抹除方法 19
2.2.1 通道熱電子注入寫入 19
2.2.2 F-N穿隧寫入 20
2.2.3 F-N穿隧抹除 20
2.3 快閃記憶體元件可靠度特性 21
2.3.1 電荷保持力 21
2.3.2 耐久力 22
第 3 章 鍺成長在多晶矽奈米線通道之快閃記憶體元件特性研究 35
3.1 研究動機與背景 36
3.2 實驗 36
3.3 結果與討論 37
3.3.1 元件汲極電流對閘極電壓作圖 37
3.3.2 元件寫入與抹除特性 38
3.3.3 元件可靠度特性 40
3.4 結論 41
第 4 章 低溫沉積二氧化鉿/氮化矽堆疊電荷捕捉層應用於鍺成長在多晶矽奈米線通道之快閃記憶體元件特性研究 56
4.1 研究動機與背景 57
4.2 實驗 57
4.3 結果與討論 59
4.3.1 元件汲極電流對閘極電壓作圖 59
4.3.2 元件寫入與抹除特性 59
4.3.3 元件可靠度特性 60
4.4 結論 62
第 5 章 低溫沉積二氧化鉿/氮化矽堆疊電荷捕捉層應用於鍺成長在多晶矽奈米線通道之無接面快閃記憶體元件特性研究 74
5.1 研究動機與背景 75
5.2 實驗 75
5.3 結果與討論 76
5.3.1 元件汲極電流對閘極電壓作圖 76
5.3.2 元件寫入與抹除特性 77
5.3.3 元件可靠度特性 78
5.4 結論 80
第 6 章 結論 89
參考文獻 91

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