隨著元件不斷的微縮，目前已來到3D立體結構FinFET製程。為了使元件特性能夠更加改善，在本論文中，主要針對高介電常數絕緣層與金屬閘極的製程來做研究。
此論文研究主要分為三個部分來探討High-k/Metal Gate製程對元件電特性之影響。
第一部分，主要的研究為MG-1金屬閘極堆疊之後增加一道PMA製程，來去探討等效功函數、臨界電壓的變化以及其他電性上的改變。從實驗結果可知，對於功函數的高低有兩種機制在互相影響；第一種是M1 diffusion，使功函數降低；第二種是Dipole formation，使功函數變高，因此臨界電壓的值可以藉由PMA的製程來去調變。且對MG-1作為金屬閘極，PMA在溫度為X+100℃時為最好的製程參數，有較好的電特性。
第二部分，主要的研究為使用不同的金屬閘極材料MG-2，與MG-1金屬閘極去做比較（MG-1：Metal A與Metal C，MG-2：Metal B與Metal C），並在沉積完後做一道PMA退火製程，來去探討這兩種金屬合金材料的熱穩定性與電特性。從結果可推測Metal B這種金屬材料相對於Metal A的熱穩定性較差。MG-2金屬閘極在PMA 溫度為X℃時有最佳的電特性。總體而言，在FinFET製程上，MG-1作為金屬閘極比MG-2來的好。
第三部分，主要的研究為使用低溫低分壓氧進行PDA來填補High-k裡的氧空缺，來去探討臨界電壓值與導通電流的變異、閘極氧化層厚度、電特性與可靠度的變化。從實驗結果可推測閘極氧化層厚度(CET)幾乎不會長厚。對NMOS元件來說，大部分電特性變得稍微差一些，臨界電壓值與變異都比較大、Ion電流較小。而對PMOS元件則大部分電性有改善，並且臨界電壓的變異變小，表示對PMOS元件的氧空缺有減少的現象，以及S.S.、Ion/Ioff ratio與DIBL特性皆有變好。而關於可靠度方面，可發現經過低溫低分壓氧的PDA製程，其NMOS與PMOS元件的可靠度皆可提升。

As device scaling, the leading edge technology is moving to FinFET process. In order to improve the FinFET performance, the thesis focuses on the study of High-k/metal gate process. There are three parts in this work to discuss the effects of High-k/metal gate process on device characteristics.
In the first study, Vth tuning by the PMA process after MG-1 gate stack is investigated. The EWF, Vth, and other electrical characteristics are discussed. It is found that there are two mechanisms affecting the work function value during the PMA process. First, Work function (WF) could be lower by M1 diffusion. Second, work function could be higher by dipole formation. Therefore, the Vth can be modified by the PMA process. PMA X+100℃ is the best annealing condition for MG-1 gate stack, which shows the best electrical performance.
In the second study, Vth tuning by different metal alloys (MG-2 vs. MG-1) is studied. （MG-1：Metal A and Metal C，MG-2：Metal B and Metal C） The thermal stability and electrical characteristics of two different metal alloys are discussed with the same PMA process. The results indicate that the thermal stability of Metal B is worse than that of Metal A. For MG-2 gate stack, PMA X℃ is the best annealing condition which shows good performance. For FinFET process, MG-1 as metal gate stack is better than MG-2.
In the last study, O2 PDA at low temperature and low partial pressure are implemented; in order to passivate oxygen vacancy in High-k. The variation of Vth and Ion, CET, other electrical characteristics and reliability are discussed. The results show that CET of O2 PDA is a little higher than that of STD. For PFinFET, most device performance can be improved. Lower Vth variation is obtained, which indicates the oxygen vacancy can be passivated. However, the improvement of device performance (Vth, σVth, Ion) for NFinFET is not achieved. For NFinFET and PFinFET, the reliability can be improved by O2 PDA.

摘要 I
致謝 III
目錄 IV
表目錄 VI
圖目錄 VII
第一章 序論 1
1.1前言 1
1.2使用FinFET結構的原因 1
1.3使用High-k/Metal Gate的原因 2
1.4臨界電壓之調變(Threshold Voltage tuning) 3
1.5 High-k裡的氧空缺之影響研究 3
1.6 GIDL機制 4
1.7論文架構 4
第二章 元件製程與量測 11
2.1 FinFET製造流程 11
2.1.1 FinFET製程 11
2.1.2本論文研究製程 12
2.2電容與電晶體電性量測 12
2.2.1 電容電性量測 12
2.2.2 電晶體電性量測 13
2.3物性分析:穿透式電子顯微鏡 14
第三章 不同金屬後退火溫度對堆疊式MG-1金屬閘極與介電層為High-k之鰭式場效電晶體特性影響研究 15
3.1研究動機 15
3.2製程與量測 16
3.3實驗結果與討論 18
3.3.1 電容電特性 19
3.3.2 使用MG-1金屬閘極堆疊經不同溫度PMA之電晶體電特性 20
3.4結論 23
第四章 金屬後退火溫度對堆疊式MG-1及MG-2金屬閘極與介電層為High-k之鰭式場效電晶體特性影響研究 37
4.1研究動機 38
4.2製程與量測 38
4.3實驗結果與討論 40
4.3.1 不同金屬閘極MG-1以及MG-2在PMA溫度為X+100℃時之電晶體電性分析 40
4.3.2 不同金屬閘極MG-1以及MG-2在PMA溫度為最佳參數時之電晶體電性與可靠度分析 43
4.4結論 46
第五章 使用低溫低分壓氧進行PDA來填補高介電層的氧空缺之鰭式場效電晶體特性影響研究 64
5.1研究動機 64
5.2製程與量測 65
5.3實驗結果與討論 67
5.3.1 使用低溫低分壓氧進行PDA來填補高介電層氧空缺之電容電特性 67
5.3.2 使用低溫低分壓氧進行PDA來填補高介電層氧空缺之電晶體電特性 68
5.3.3 使用低溫低分壓氧進行PDA來填補高介電層氧空缺之電晶體可靠度 70
5.4結論 72
第六章 結論 87
參考文獻 89

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