鍺相較於矽而言，電子的遷移率可提升兩倍、電洞的遷移率可以提升至四倍，故利用純鍺基板以及high-k材料來達成超薄等效氧化層厚度，以及更高的載子遷移率，對於通道電流傳輸可以大大改善。但鍺半導體材料製程也存在許多困難，在400℃下產生易揮發氣體不耐高溫且容易水解，鍺擴散造成的漏電流以及氧化鍺的界面工程皆是我們致力於改善的目標。
本論文的研究使用純鍺基板，於ALD (Atomic Layer Deposition System)中堆疊不同的薄膜緩衝層來提升鍺金氧半元件的電特性，其中第一部分，使用二氧化鋯(ZrO2)做為high-k材料，並且在GeO2界面層與ZrO2介電層之間沉積一層鉿薄膜和鋯薄膜緩衝層(Hf-rich and Zr-rich Buffer Layer)並探討其電性上的改變。實驗結果可以發現，加入鋯薄膜緩衝層的電容元件，等效氧化層厚度是最低的4.3 Å，閘極漏電流則會增加，維持在10-1 (A/cm2)，且得到的Ge基板與GeO2界面層之間的界面品質較差。而加入鉿薄膜緩衝層的電容元件，等效氧化層厚度會增加至4.9 Å，但能夠降低閘集漏電流，並且得到較好的界面品質。從XPS圖中也可以推測，鋯薄膜緩衝層會嚴重消耗掉GeO2界面層，使得閘集漏電流增加和界面品質變差，鉿薄膜緩衝層會與GeO2界面層產生混合，形成一層較厚且較緻密的HfGeOX界面層，因此能夠得到低的閘極漏電流和好的界面品質。而加入鉿薄膜和鋯薄膜緩衝層的元件在其他電性上的的表現如Hysteresis以及Reliability也是不錯的。
第二部分中，我們以不同的溫度沉積ZrO2介電層，分別為2500C、3000C和3500C，比較這三種溫度下沉積之ZrO2介電層在電性上的差異。實驗結果可以發現，以3000C沉積之ZrO2介電層，EOT約為4.7 Å，雖然閘極漏電流會增加，但是因為有高的氧含量，少的Oxide traps，而且與GeO2界面層之間有較好的混合，在Hysteresis，Stress induced Vfb voltage shift，以及SILC的表現上明顯優於以2500C和3500C沉積之ZrO2介電層。
第三部分中，延續上兩部分所得到的結果，利用3000C沉積ZrO2介電層並加入鉿薄膜和鋯薄膜緩衝層來製作電晶體元件，探討其在電特性上的差異。實驗結果可以發現，ZrO2介電層加入鉿薄膜緩衝層時，得到的元件電特性也較單層ZrO2介電層和ZrO2介電層加入鋯薄膜緩衝層的元件特性好，有較大的汲極飽和電流和較小的關閉電流，其中電子遷移率約350cm2/V-s，在Reliability特性上也有不錯的表現。

Ge possesses two times electron mobility and four times hole mobility compared to Si. So we use Ge substrate and high-k material to obtain ultra-thin EOT, to achieve high mobility and drain current. However, using Ge material will face many challenges. It is easy for Ge oxide to be volatilized and hydrolyzed at 4000C. Ge out-diffusion induced gate leakage and Ge oxide quality is our first priority which is needed to be improved immediately.
In this thesis, different buffer layer is deposited by ALD (Atomic Layer Deposition System) to improve the electrical characteristics of Ge MOS devices. In the first part, We use ZrO2 as high-k material, and deposit Hf-rich and Zr-rich buffer layer between ZrO2 dielectric and GeO2 interfacial layer on Ge MOSCAPs. For Ge MOSCAPs with Zr-rich buffer layer, the EOT is the thinnest, 4.3 Å, but the gate leakage current is increased, around 10-1 A/cm2, and the interfacial quality between Ge substrate and GeO2 interfacial layer is poor. For Ge MOSCAPs with Hf-rich buffer layer, the EOT is increased to 4.9 Å, but the gate leakage current can be reduced, and better interfacial quality can be achieved. From XPS, we consider that Zr-rich buffer layer will seriously consume GeO2 interfacial layer, and cause the gate leakage current increased, and poor interfacial quality. However, Hf-rich buffer layer will incorporate into GeO2 interfacial layer, and then form a thicker and denser HfGeOX interfacial layer, so it can achieve lower gate leakage current and better interfacial quality. Ge MOS devices with Hf-rich and Zr-rich buffer layer can also achieve small hysteresis and good reliability characteristics.
In the second part, we use different temperature to deposit ZrO2 dielectric, 2500C, 3000C and 3500C, respectively, and then discuss the difference between the electrical characteristics of Ge MOSCAPs with ZrO2 dielectric at different temperature. For ZrO2 dielectric deposited at 3000C, EOT is about 4.7 Å, although the gate leakage current is increased, the characteristics of hysteresis, stress induced flat-band voltage shift, and SILC is obviously better than ZrO2 dielectric deposited at 2500C and 3500C due to higher oxygen content, fewer oxide traps, and better intermixing between GeO2 interfacial layer and ZrO2 dielectric.
In the third part, we combine the results of the above two experiments, and use 3000C to deposit ZrO2 dielectric with Hf-rich and Zr-rich buffer layer on Ge MOSFETs, and then discuss the difference of the electrical characteristics. For ZrO2 dielectric with Hf-rich buffer layer, the electrical characteristics are better than ZrO2 dielectric with Zr-rich buffer layer and without buffer layer, it can achieve higher saturation drain current and lower off current, the mobility is about 350 cm2/V-s, and it can also achieve good reliability characteristics.

摘要 2
致謝 4
目錄 5
表目錄 9
圖目錄 10
第一章 序論 16
1.1前言 16
1.2使用鍺基板作為載子通道材料 16
1.3高介電係數(High-K)介電材料導入的原因 17
1.4高介電係數(High-K)材料的選擇 18
1.5 界面缺陷鈍化(Interface defect passivation) 19
1.6 界面層的形成方式 20
1.7 原子層沉積系統(Atomic Layer Deposition System) 22
1.8 論文架構 23
第二章 元件製程與量測 30
2.1鉿/鋯薄膜緩衝層及高溫沉積之ZrO2介電層的純鍺基板MOSCAP元件及PMOSFET元件製程流程 30
2.1.1實驗前晶片清洗 30
2.1.2以H2O plasma成長之GeO2界面層與閘極介電層沉積 31
2.1.3金屬閘電極與接觸電極的形成 31
2.1.4源極(Source)、汲極(Drain)、基極(Base)的形成 32
2.1.5接出金屬導線、燒結 32
2.2電性量測 33
2.2.1金氧半電容的量測 33
2.2.2金氧半電晶體的量測 36
2.3 物性分析 37
2.3.1 X光繞射儀 37
2.3.2 X射線光電子能譜儀 38
2.3.3穿透式電子顯微鏡 38
第三章 ZrO2介電層含鉿/鋯薄膜緩衝層對鍺金氧半電容電特性研究 42
3.1研究動機 43
3.2製程與量測 44
3.2.1製程條件 44
3.2.2量測參數 45
3.3實驗結果與討論 46
3.3.1 ZrO2介電層含鉿/鋯薄膜緩衝層之鍺金氧半電容電特性分析 46
3.3.2 ZrO2介電層含鉿/鋯薄膜緩衝層之鍺金氧半電容物理特性分析 51
3.4結論 54
第四章 高溫沉積之ZrO2介電層對鍺金氧半電容電特性研究 67
4.1研究動機 67
4.2製程與量測 69
4.2.1製程條件 69
4.2.2量測參數 70
4.3實驗結果與討論 70
4.3.1高溫沉積之ZrO2介電層對金氧半電容電特性分析 70
4.3.2高溫沉積之ZrO2介電層之金氧半電容物理特性分析 75
4.4結論 76
第五章 高溫沉積之ZrO2介電層含鉿/鋯薄膜緩衝層對鍺金氧半電晶體電特性研究 85
5.1研究動機 86
5.2製程與量測 86
5.2.1製程條件 86
5.2.2量測參數 87
5.3實驗結果與討論 88
5.3.1 ZrO2介電層含鉿/鋯薄膜緩衝層之鍺金氧半電晶體電特性分析 88
5.4結論 92
第六章 結論與展望 108
6.1結論 108

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