隨著半導體產業發展使矽電晶體的尺寸縮小已到限制，所以勢必要引入新的材料或創新的結構。由於鍺有比矽高的電子和電洞遷移率，所以被用來作為電晶體的通道材料。為了提升鍺電晶體元件的特性，有一層高品質的界面層是需要的。因此提供一個精確和快速的量測方法去偵測界面缺陷密度和深層缺陷是值得研究的主題。本論文以電荷汲引原理為基礎，提出了多種量測技術用來探測缺陷密度分佈。
第一部分為界面層氫處理與微波退火電晶體元件，可以得到經過氫處理和微波退火的元件，具有較低的界面缺陷密度，較好的界面層品質。電性上有較大的驅動電流和較低的關閉電流，在載子遷移率上也有更好的表現。而邊緣陷阱縱深分佈上，氫處理可以有效的改善縱深小於0.8 nm缺陷密度；而微波退火可以顯著的改善縱深大於1 nm的缺陷密度。
第二部分為利用電荷汲引技術去比較不同的介電層ZrO2和HfON電晶體的界面缺陷密度、邊緣陷阱密度、和應力誘發缺陷的增生。結果顯示了ZrO2元件有較高的界面缺陷密度但有較低的邊緣缺陷密度；HfON元件有較低的界面缺陷密度但有較高的邊緣缺陷密度。說明了ZrO2元件在可靠度分析上，能抑制電荷在介電層被捕捉，主要是因為具有較低的邊緣缺陷密度所致。
第三部分為利用電荷汲引技術去量測有無Hf緩衝層電晶體的界面缺陷密度、邊緣陷阱密度、和應力誘發缺陷的增生。經電荷汲引技術來看可發現有Hf緩衝層的元件，有較低界面陷阱密度和邊緣陷阱密度，得到有較佳的界面品質和介電層，而電性上也都有改善。經由NBTI和PBTI可靠度分析，從電荷汲引技術發現NBTI對界面層的破壞較嚴重；而PBTI則是在介電層有嚴重的破壞，發現有Hf緩衝層元件都有較好的表現，主要是有較好的界面層和介電層品質。

As the scaling of silicon metal-oxide-semiconductor (MOSFET) approach to its limitation with the development of semiconductor industry, novel materials and innovative device structures need to be introduced in future. Ge is promising for a channel material in MOSFET, owing to its high hole and electron mobility. A high quality interface layer is necessary to improve characteristics on Ge-MOSFETs device. Hence, an accurate and quick measurement to detect interface trap density and distribution of bulk traps should be a valuable research topic. Several measurement techniques based on the charge pumping are proposed to detect trap density distributions.
In the first study, interface layer with hydrogen treatment and microwave annealing Ge MOSFET devices obtain lower interface trap density and better interface layer quality than without one. The electrical characteristic have higher drive current, mobility, and lower off current, due to interface layer with hydrogen treatment can repair interface traps and microwave annealing can improve PN junction. On the other hand, hydrogen treatment can improve traps density less than depth about 0.8 nm and microwave annealing can obviously reduce traps density higher than depth about 1 nm from distribution profile of border traps density.
In the second study, the interface trap density, bulk density and stress induced trap generation of Ge-pMOSFETs with ZrO2 and HfON gate dielectrics are extracted and compared by CP technique. Results show that ZrO2 device has higher interface trap density but lower bulk trap density than HfON device, which implies that ZrO2 device has inferior Ge/dielectric interface but high quality dielectric bulk. The improved reliability characteristics in ZrO2 device can be attributed to the low preexisting bulk trap density which suppresses charge trapping in the dielectric bulk.
In the last study, charge pumping technique is used to detect interface and bulk trap distribution and stress induced trap generation of Ge-pMOSFETs with and without Hf buffer layer (HBL). The charge pumping technique confirm that device with HBL has lower interface and bulk traps density than device without, which show electrical characteristic can be improved. Results show that device with HBL has better performance from NBTI and PBTI reliability analysis because of it has higher quality of interface characteristics and dielectric bulk.

摘要 I
致謝 III
目錄 IV
圖目錄 XII
表目錄 XVI
第一章 序論 1
1.1 前言 1
1.2 使用High-K介電材料的原因 1
1.3 High-K介電材料的選擇 2
1.4 純鍺基板作為載子通道 4
1.5 鍺氧化物的性質 5
1.6 電荷汲引量測技術 6
1.7 論文架構 6
第二章 應用電荷汲引量測技術分析High-k介電層電晶體陷阱分佈 12
2.1研究動機 12
2.2界面陷阱密度與能量分佈 13
2.2.1 基本電荷汲引量測技術 13
2.2.2 陷阱捕捉截面(Capture Cross Section, σ)的計算 15
2.2.3 High-κ電晶體界面陷阱密度能量分佈 16
2.2.4 量測結果與討論 17
2.3邊緣陷阱密度縱深分佈的量測 18
2.3.1 高介電係數電晶體的邊緣陷阱 18
2.3.2 量測方法與量測裝置 18
2.3.3 縱深分布公式與計算 19
2.2.4量測結果與討論 21
2.4 結論 21
第三章 介面層經氫氣處理與微波退火對Ge MOSFET元件特性研究 33
3.1 研究動機 33
3.2 製程與量測 34
3.2.1 製程條件 34
3.2.2 量測參數 35
3.3 實驗結果與討論 36
3.3.1 界面層氫處理與微波退火之電晶體元件界面特性 36
3.3.2界面層氫處理與微波退火之電晶體元件負定電壓電應力 39
3.4 結論 40
第四章 不同閘極介電層ZrO2和HfON的鍺金氧半電晶體 52
4.1 研究動機 52
4.2 製程與量測 53
4.2.1 製程條件 53
4.2.2 量測參數 54
4.3 實驗結果與討論 54
4.3.1不同介電層電晶體元件之特性分析 54
4.3.2不同介電層電晶體元件之負定電壓電應力 55
4.3.3不同介電層電晶體元件之通道熱載子應力 57
4.4 結論 59
第五章 有無Hf緩衝層之MOSFET元件特性研究 70
5.1 研究動機 70
5.2製程與量測 71
5.2.1製程條件 71
5.2.2 量測參數 72
5.3實驗結果與討論 72
5.3.1有無Hf緩衝層電晶體元件之特性分析 72
5.3.2有無Hf緩衝層電晶體元件之NBTI分析 74
5.3.3有無Hf緩衝層電晶體元件之PBTI分析 75
5.4 結論 77
第六章 結論與展望 89
6.1 結論 89
6.2 未來展望 90
參考資料 91

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