鍺相較於矽而言，電子的遷移率可提升兩倍、電洞的遷移率可以提升至四倍，故利用純鍺基板以及high-k材料來達成超薄等效氧化層厚度，以及更高的載子遷移率對於通道電流傳輸可以大大改善。但鍺半導體材料製程也存在許多困難，在400℃下產生易揮發氣體不耐高溫且容易水解，鍺擴散造成的漏電流以及氧化鍺的介面工程皆是我們致力於改善的目標。因此，我們希望藉由鉿薄膜緩衝層來改善介面，並且使用高介電係數的材料氧化鋯來改善電特性，最後再利用不同的熱退火處理來優化鍺金氧半電晶體的電特性。
本論文的研究以使用純鍺基板，於ALD (Atomic Layer Deposition System)中堆疊不同的high-k以提升鍺基板元件的特性，其中第一部分，使用氮氧化鉿(HfON)做為high-k材料製作電晶體，並且在介面GeO2與氮氧化鉿中間沉積一層薄的鉿薄膜緩衝層(Hf film Buffer Layer)探討其電性上的改變。實驗結果可以發現，介電層為氮氧化鉿含鉿薄膜緩衝層，其等效反轉氧化層厚度(Tinv)為7 Å，閘極漏電流則維持在2x10-3 A/cm2，並且有更大的驅動電流以及較高的載子遷移率以及改善介面。從XRD圖中也可以推測，high-k層中的HfON因為Ge的擴散，增進形成一介電係數非常高的Tetragonal phase。
第二部分中，延續第一部分提到的鉿薄膜緩衝層來改善GeO2與介電層的介面，並且摻入二氧化鋯(ZrO2)材料進入high-k層中，比較ZrO2與HfON以及交互堆疊層在電性上的差異。實驗結果可以發現，在介電層摻入材料二氧化鋯的結構不論是下層HfON上層ZrO2或者兩者交互堆疊成的HfO-ZrO co-deposition，在電性上都表現的比單層介電層HfON來的突出。另外我們也發現使用單層的介電層材料HfON在元件的可靠度特性上都會比堆疊層要來的好。
第三部分中，延續上兩部分所得到的結果，利用鉿薄膜緩衝層以及下層HfON上層ZrO2作介電層製作電晶體元件，最後比較燒結(Sinter) 、微波退火(Microwave annealing)及雷射退火(Laser annealing)其在電特性上的差異。實驗結果可以發現，利用雷射退火可以增加元件的驅動電流，而微波退火主要可以改善介面進而降低元件的關閉電流。

Ge possesses two times electron mobility and .four times hole mobility compared to Si. Using Ge substrate and high-k material to obtain ultra-thin EOT, to achieve high mobility and drain current. However, using Ge material will face many challenges. It is easy for Ge oxide to be volatilized and hydrolyzed at 400°C. Ge out-diffusion induced gate leakage and Ge oxide quality is our first priority which is needed to be improved immediately. First, Hf film buffer layer can improve the interfacial layer. ZrO with a higher dielectric constant is used to achieve ultra-thin EOT and improve electrical characteristics of Ge MOS devices. At last, different annealing processes is performed to optimize electrical characteristics of Ge MOSFETs.
In this thesis, different high-k materials are deposited by an ALD on Ge substrate to improve the electrical characteristics of MOS device. In the first part, HfON is used as a high-k material. An Hf film buffer layer is deposited between HfON and GeO2, and the change of electrical characteristics is discussed. One can conclude that if HfON with Hf film buffer layer is chosen as a high-k material, 0.7 nm EOT can be achieved, and gate leakage is about 2x10-3 A/cm2. Moreover, it has higher drain current and mobility due to improved interfacial layer. Ge out diffusion into HfON can enhance tetragonal phase, resulting in a higher dielectric constant.
In the second part, ZrO2 and HfON are integrated as high-k dielectric stacks, and the electrical characteristic are discussed as well. The Hf film buffer layer as studied in the first part is also used. HfON/ZrO2 and HfO-ZrO co-deposition exhibit better electrical characteristic than that of single HfON layer. However, it is found that the reliability of single HfON layer is better than that with high-k dielectric stacks.
In the third part, the Hf film buffer layer and HfON/ZrO2 stack are applied to Ge MOSFETs. Difference annealing processes such as sinter, microwave annealing, and laser annealing are compared. In conclusion, laser annealing can improve drain current of Ge MOSFETs. Interface quality can be improved by microwave annealing, and then off current is reduced.

摘要 II
目錄 IV
表目錄 VII
圖目錄 VIII
第一章 緒論 1
1.1前言 1
1.2使用鍺基板作為載子通道材料 1
1.3高介電係數(High-K)介電材料導入的原因 2
1.4高介電係數(High-K)材料的選擇 3
1.5 界面缺陷鈍化(Interface defect passivation) 4
1.6 介面層的形成方式 5
1.7 原子層沉積系統(Atomic Layer Deposition System) 6
1.8微波退火的機制 7
1.9雷射退火的機制 8
1.10 論文架構 8
第二章 元件製程與量測 16
2.1鉿薄膜緩衝層及HfON堆疊ZrO2高介電層經由不同熱處理之純鍺基板PMOSFET元件製程流程 16
2.1.1實驗前晶片清洗 16
2.1.2以H2O plasma製程方式之GeO2介面層製程與閘極介電層成長 17
2.1.3金屬閘電極與接觸電極的形成 17
2.1.4源極(Source) 、汲極(Drain)的形成 17
2.1.5接出金屬導線、鈍化、燒結 18
2.2電性量測 18
2.2.1金氧半電晶體的量測 18
2.3物性分析 20
2.3.1X光繞射儀 20
2.3.2X射線光電子能譜儀 20
2.3.3穿透式電子顯微鏡 21
第三章　氮氧化鉿鍺金氧半電晶體之鉿薄膜緩衝層元件電特性研究 24
3.1研究動機 24
3.2製程與量測 25
3.2.1製程條件 25
3.2.2量測參數 26
3.3實驗結果與討論 27
3.3.1氮氧化鉿鍺金氧半電晶體之鉿薄膜緩衝層元件電特性分析 27
3.3.2氮氧化鉿鍺金氧半電晶體之鉿薄膜緩衝層元件物理特性分析 29
3.4結論 30
第四章　氮氧化鉿及氧化鋯堆疊之金氧半電晶體的元件特性研究 46
4.1研究動機 46
4.2製程與量測 47
4.2.1製程條件 47
4.2.2量測參數 48
4.3實驗結果與討論 49
4.3.1氮氧化鉿與氧化鋯之鍺金氧半電晶體之元件電特性分析 49
4.3.2氮氧化鉿與氧化鋯之鍺金氧半電晶體之元件物理特性分析 52
4.4結論 53
第五章 不同的熱處理對金氧半電晶體的元件電特性研究 69
5.1研究動機 69
5.2製程與量測 70
5.2.1製程條件 70
5.2.2量測參數 71
5.3實驗結果與討論 71
5.3.1不同熱處理之鍺金氧半電晶體之元件電特性分析 71
5.4結論 74
第六章 結論與展望 89
6.1結論 89
6.2未來展望 90
參考文獻 91

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