現代電子產品功能不斷擴張，強調多功能、體積小及重量輕等訴求，而消費者購買產品帶動經濟市場，驅使電子業做出更好產品，造成產品中的電晶體必須不斷微縮以符合市場需求，而在微縮過程中遭遇越來越多設計電晶體的困難，無論是元件結構上的短通道效應或是製程上的挑戰都是很重要的研究議題。
因此在本篇論文中，提出了混合式無接面式電晶體搭配溝槽結構作探討；無接面電晶體的特色是在源極、汲極和通道都是同樣摻雜的元素和濃度，可避免傳統電晶體因為接面所導致的短通道效應影響，並且讓製程更簡單；使用混合式結構是藉由基板與通道在垂直方向上產生的接面造成等效通道厚度減少，也因此可以在矽晶片上直接製造出無接面電晶體並保持很好的電特性，而溝槽狀結構則是藉由非等向性蝕刻使電晶體通道變薄，提升閘極對通道的控制能力。在設計電晶體的過程中，採用沉積較厚的非晶矽，接著有效退火、結晶獲得較大晶粒尺寸的多晶矽以提升元件主動層的薄膜品質，再藉由乾式蝕刻的非等向性特性來達到超薄的溝槽狀通道。
本篇論文開發出混合式無接面電晶體結構搭配溝槽式通道有著omega結構閘極和奈米線 (Nanowires) 結構之多晶矽無接面薄膜電晶體。此元件展現了極佳的電特性，像是陡峭之次臨界擺幅 (Subthreshold swing, SS) 109 mV/dec.、較高的開關電流比 (Ion/Ioff current ratio > 108 )、較低的汲極引致能障下降值 (Drain-induced barrier lowering, DIBL)為 9 mV/V，此外本結構對I-V特性對溫度有加以探討，接著再使用T-cad模擬軟體與實際數據作分析比較，驗證模擬結果與實驗數據相符。
提出此混合式無接面薄膜電晶體搭配溝槽狀結構有良好的電特性且製程非常簡單容易，因此非常有機會在應用在未來三維堆疊結構與低消耗功率元件上做搭配。

Modern electronic devices become more and more useful, emphasizing on multifunctional, small size, light weight, etc. The rapid development in electronic industries has led to considerable increases in consumer’s purchasing desire, and triggered electronics industry to improve its products. However, the expectation of transistors in scaling suffered more and more difficult to design, whether the short channel effect in devices or the challenge of process are very important research issues.
In this thesis, the hybrid junctionless field-effect-transistors with trench structure are proposed and fabricated; the special fabrication of junctionless is the same doping concentration and doping type in channel, source, and drain, so the channel to source and the channel to drain have no junction. And these devices can avoid the short channel effects and simplify the fabrication compared to inversion mode transistors. The hybrid structure makes the thinner effective channel thickness owing to the depletion layer by the channel and substrate; it can easily fabricate devices on the bulk Si wafer and keep the good electrical characteristics. Then, the trench structure improves the ability of gate control owing to the thin channel by the anisotropic etching process. In the fabrication, the annealing after depositing the thick amorphous silicon gets the larger poly silicon grain size, and it also can improve the active area film quality; finally, it achieves the thin trench channel by the reactive-ion etching process.
The hybrid poly silicon channel junctionless field-effect-transistors with trench structure have ten nanowires with omega gate structure. The performance of the hybrid junctionless field-effect-transistors with trench structure is excellent with the small sub-threshold swing (SS) (109mV/dec.), the high current ratio (Ion/Ioff current ratio > 108), and negligible DIBL (9mV/V); then, discuss the electrical characteristics in variable temperature with every 25oC as a step from the 25oC to 200oC, analyze those devices by using the Arrhenius sweeps. Finally, the last result shows the TCAD simulation to assist the analysis and confirms the measured basic electric characteristics.
The proposed hybrid JL-FETs with trench structure not only the easy fabrication but also the good characteristics are highly promising for use in advanced system-on-chip and 3D stacked ICs applications.

中 文 摘 要 I
Abstract III
Acknowledge V
Contents VII
Figure Captions IX
Table XV
Chapter 1 1
Introduction 1
1-1 The MOSFET Scaling 1
1-2 Introduction of Junctionless Device 5
1-2 Motivation 13
1-3 Thesis Organization 17
Chapter 2 19
Junctionless Mechanism 19
2-1 Conduction Mechanisms 19
2-2 Short Channel Effects in Junctionless transistor 23
2-3 The Temperature Performance of Junctionless 24
High temperature 24
Low temperature 26
2-4 The Design Guideline of Junctionless Transistor 28
Chapter 3 30
Device Fabrication 30
Chapter 4 33
Characteristics Analysis 33
4-1 Device Structure Images Analysis 33
4-1-1 SEM image and AFM image 35
4-1-2 SIMS profile and TEM image 38
4-2 Device Electrical Analysis 41
4-2-1 Basic Electrical Analysis 42
4-2-2 Device Temperature Performance 47
4-3 Device Simulation 54
4-3-1 Device Structure Simulation 54
4-3-2 Device Simulation Analysis 57
Chapter 5 62
Conclusion 62
Reference 64

Reference
Chapter 1
[1-1] International Roadmap Committee, “International Technology Roadmap for Semiconductors: 2013 Edition Executive Summary,” Semiconductor Industry Association, San Francisco, CA, 2013.
[1-2] S. E. Thompson and S. Parthasarthy, “Moore’s law: The future of Si microelectronics,” Mater. Today, vol. 9, no. 6, pp. 20–25, Jun. 2006.
[1-3] W. Arden, M. Brillouet, P. Cogez, M. Graef, B. Huizing, and R. Mahnkopf, More-than-Moore, White Paper. [Online].
Available: http://www.itrs.net/Links/2010ITRS/IRC-ITRS-MtM-v2%203.pdf.
[1-4] D. J. Frank, R. H. Dennard, E. Norwak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, “Device scaling limits of Si MOSFETs and their application dependencies,” Proc. IEEE, vol. 89, no. 3, pp. 259–288, Mar. 2001.
[1-5] J. R. Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, “Generalized guide to MOSFET miniaturization,” IEEE Electron Devices Lett., vol. EDL-1, no. 1, pp. 2–4, 1980.
[1-6] Peide Ye, Devices Challenges for 7nm CMOS Technology and Beyond, International Electron Devices Meeting (IEMD) at San Francisco, Dec. 14, 2014.

[1-7] T. Ito, K. Suguro, M. Tomura, T. Taniguchi, Y. Ushiku, T. linuma, T. Itani, M. Yoshioka, T. Owada, Y. Imaoka, H. Murayama and T. Kusuda, "Flash Lamp Annealing Technology for Ultra-shallow Junction Formation," in International Workshop on Junction Technology,2002, pp. 23–26.
[1-8] I. Ok, K.-W. Ang, C. Hobbs, R.H. Baek, C.Y. Kang, J. Snow, P. Nunan, S. Nadahara, P.D. Kirsch, and R. Jammy, "Conformal, low-damage shallow junction technology (Xj:5 nm) with optimized contacts for FinFETs as a Solution Beyond 14 nm Node," in 12th International Workshop on Junction Technology, 2012, pp. 29–34.
[1-9] J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Ravazi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[1-10] S. Migita, Y. Morita, M. Masahara, and H. Ota, “Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm),” in Proc. Int. Electron. Devices Meeting, Dec. 2012, pp. 191–194.
[1-11] H.-C. Lin, C.-I. Lin, Z.-M. Lin, B.-S. Shie, and T.-Y. Huang, “Characteristics of planar junctionless poly-Si thin-film transistors with various channel thickness,” IEEE Trans. Electron Devices, vol. 60, no. 3, pp. 1142–1148, Mar. 2013.
[1-12] B. Kim, S. H. Lim, D. W. Kim, T. Nakanishi, S. Yang, J. Y. Ahn, H. M. Choi, K. Hwang, Y. Ko, and C. J. Kang, “Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash,” in Proc. IEEE International. Reliability Physics Symposium, Apr. 2011, pp. 126–129.
[1-13] J. Kim, A. Hong, S. M. Kim, E. Song, J. H. Park, J. Han, S. Choi, D. Jang, J. T. Moon, and K. Wang, “Novel Vertical-Stacked-ArrayTransistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (Solid State Drive),” in VLSI T ’09, 2009, pp. 186 –187.
[1-14] M.-H. Han, C.-Y. Chang, H.-B. Chen, J.-J. Wu, Y.-C. Cheng, and Y.-C. Wu, “Performance comparison between bulk and SOI junctionless transistors,” IEEE Electron Device Lett., vol. 34, no. 2, pp. 169–171, Feb. 2013.
[1-15] Y.-C. Cheng, H.-B. Chen, J.-J. Su; C.-S. Shao ; Thirunavukkarasu, V., C.-Y. Chang, and Y.-C. Wu, “Characteristics of a novel poly-Si P-channel junctionless thin-film transistor with hybrid P/N-Substrate,” IEEE Electron Device Lett., vol. 36, no. 2, pp.159–161, Feb. 2015.
[1-16] M.-S. Yeh, Y.-C Wu, M.-H. Wu, M.-H. Chung, Y.-R. Jhan, and M.-F. Hung, “Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure,” IEEE Electron Device Lett., vol. 36, no. 2, pp. 150–152, Feb. 2015.

Chapter 2
[2-1] C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “High temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 620–625, Mar. 2010.
[2-2] J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications. New York, NY, USA: Springer-Verlag, 2011, pp. 187–200.
[2-3] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electron., vol. 54, no. 2, pp. 97–103, Feb. 2010
[2-4] P. Razavi, G. Fagas, I. Ferain, R. Yu, S. Das, and J. P. Colinge, “Influence of channel material properties on performance of nanowire transistors,” Journal of Applied Physics, vol. 111, no. 12, pp. 124509-1–124509-8, 2012.
[2-5] D.-Y. Jeon, S. J. Park, M. Mouis, S. Barraud, G.-T. Kim, and G. Ghibaudo, “Low-temperature electrical characterization of junctionless transistors,” Solid State Electronics, vol. 80, pp. 135–141, Feb. 2013.
[2-6] M. de Souza, M. A. Pavanello, R. D. Trevisoli, R. T. Doria, and J. P. Colinge, “Cryogenic operation of junctionless nanowire transistors,” IEEE Electron Device Lett., vol. 32, no. 10, pp. 1322–1324, Oct. 2011.
[2-7] A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Junctionless nanowire transistor (JNT): Properties and design guidelines,” in Proc. 34th IEEE Eur. Solid-State Device Res. Conf., Aug. 2010, pp. 357–360. .
[2-8] A. Gnudi, S. Reggiani, E. Gnani, and G. Baccarani, “Analysis of threshold voltage variability due to random dopant fluctuations in junctionless FETs,” IEEE Electron Device Lett., vol. 33, no. 3, pp. 336–338, Mar. 2012.
[2-9] G. Leung and C. O. Chui, “Variability impact of random dopant fluctuation on nanoscale junctionless FinFETs,” IEEE Electron Device Lett., vol. 33, no. 6, pp. 767–769, Jun. 2012.
[2-10] S.-J. Choi, D.-I. Moon, S. Kim, J. P. Duarte, and Y.-K. Choi, “Sensitivity of threshold voltage to nanowire width variation in junctionless transistors,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 125–127, Feb. 2011.
[2-11] G. Leung and C. Chui, “Variability of inversion-mode and junctionless FinFETs due to line edge roughness,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1489–1491, Nov. 2011.
[2-12] J.-P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazarov, and R. T. Doria, “Reduced electric field in junctionless transistors,” Applied Physics Lett., vol. 96, no. 7, p. 073510, Feb. 2010.

Chapter 4
[4-1] M.-S. Yeh, Y.-C Wu, M.-H. Wu, M.-H. Chung, Y.-R. Jhan, and M.-F. Hung, “Characterizing the Electrical Properties of a Novel Junctionless Poly-Si Ultrathin-Body Field-Effect Transistor Using a Trench Structure,” IEEE Electron Device Lett., vol. 36, no. 2, pp. 150–152, Feb. 2015.
[4-2] Y.-C. Cheng, H.-B. Chen, J.-J. Su; C.-S. Shao ; Thirunavukkarasu, V., C.-Y. Chang, and Y.-C. Wu, “Characteristics of a novel poly-Si P-channel junctionless thin-film transistor with hybrid P/N-Substrate,” IEEE Electron Device Lett., vol. 36, no. 2, pp.159–161, Feb. 2015.
[4-3] C.-W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “Performance estimation of junctionless multigate transistors,” Solid-State Electron., vol. 54, no. 2, pp. 97–103, Feb. 2010.
[4-4] A. J. Walker, S. B. Herner, T. Kumar, and E.-H. Chen, “On the conduction mechanism in polycrystalline silicon thin-film transistors,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1856–1866, Nov. 2004.
[4-5] J. P. Colinge, C. Lee, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, A. Kranti, and R. Yu, Junctionless Transistors: Physics and Properties, Semiconductor-On-Insulator Materials for Nanoelectronics Applications. New York, NY, USA: Springer-Verlag, 2011, pp. 187–200.