近在元件日漸微縮的趨勢下，平面式元件微縮空間有限，使得元件的密度難以再提升而且製程上也變的棘手。因此要增加元件密度以及使電特性提高是目前重要的課題。而目前已經有許多解決方法被提出，像是使用高介電常數材料的應用、奈米線通道的結構、無接面快閃記憶體元件的應用及三維堆疊陣列等等。本篇論文以使用了低溫的二氧化矽當作穿隧層用在奈米線通道結構以及可堆疊式電荷捕捉式快閃記憶體元件，以及高介電常數材料做能帶工程的應用，目的是為了減少熱預算與增加單位面積之元件密度。
第一個實驗室使用了較低溫的感應耦合電漿化學氣相沉積(ICPCVD)成長出來的氧化層來當我們的穿隧層(Tunneling Layer)，以及使用高介電常數材料做能帶工程應用來當我們的電荷捕捉層，而結構上都是使用奈米線通道式的結構，可以發現使用低溫的感應耦合電漿化學氣相沉積(ICPCVD)成長出來的氧化層與使用急速升溫退火爐(KORONA)成長出來的氧化層擁有差不多好的電特性，而使用二氧化鉿/氮化矽堆疊的電荷捕捉層比單層的氮化矽擁有較快的寫入抹除速度，在可靠度上面也有所改善，因此能帶工程對元件的特性的確有所改善。
第二個實驗也是使用了較低溫的感應耦合電漿化學氣相沉積(ICPCVD)成長出來的氧化層來當我們的穿隧層(Tunneling Layer)，以及使用高介電常數材料做能帶工程應用來當我們的電荷捕捉層，而結構上則是使用了無接面奈米線通道式的結構，可以看到無接面式元件它的確都擁有不錯的寫入特性，能帶工程在寫入特性、記憶窗大小及可靠度特性上都有所改善，因此希望可以將ICPCVD成長的電荷穿隧層應用到未來3-D堆疊結構上。
第三個實驗就是將ICPCVD成長的電荷穿隧層應用到可堆疊式閘極元件上面，並且探討能帶工程在這種可堆疊式閘極元件上是否能有特性的改善，可以發現能帶工程在這種可堆疊式閘極元件上的確改善了他的寫抹速度、電荷保持力及電荷耐久力的特性，但發現到所有元件在可靠度上的表現並不是很好，雖然ICPCVD成長的二氧化矽應用在奈米線結構元件上特性表現得不錯，但是在這種可堆疊式閘極元件上ICPCVD成長的二氧化矽還有很大的改善空間。

The scaling trend of flash device is limited by the dimension of planar device, which makes the process flow more complex. How to improve the operational characteristics and increase the device density at the same time become two of the most important issues. Some approaches have been reported such as high-k material, nanowire channel structure, junctionless (JL) channel and 3D array flash memory devices. In this thesis, a low temperature formed SiO2 is proposed as tunneling layer for nano-wire and stacked vertical gate structure charge trapping (CT) flash memory devices. The purposes are to reduce thermal budget and increase device density.
In the first study, a low temperature formed SiO2 is proposed to replace conventional high temperature SiO2 as tunneling layer. HfO2/Si3N4 stacked trapping layers are implemented to improve the operational characteristics of nano-wire inversion mode flash device. It is found that operational characteristics such as program/erase (P/E) speed、retention and endurance characteristics of low temperature formed SiO2 are as good as those with high temperature formed SiO2. HfO2/Si3N4 stacked trapping layers device has better P/E speed and good reliability characteristics truely.
In the second study, a low temperature formed SiO2 is used as tunneling layer and HfO2/Si3N4 stacked trapping layers to improve the operational characteristics of nano-wire junctionless device. It is found that HfO2/Si3N4 stacked trapping layers device has good P/E speed、memory window and reliability characteristics. Therefore, low temperature formed SiO2 is promising to be applied to 3-D stacked device.
In the last study, low temperature formed SiO2 is applied to stacked vertical gate structure. Effect of HfO2/Si3N4 stacked trapping layers on operational characteristics of the stacked vertical gate device is also studied. It is found that HfO2/Si3N4 stacked trapping layers device improves its P/E speed、retention and endrance characteristics truly. However, the reliability characteristics of all devices are not good enough. Therefore, improvement of ICPCVD formed SiO2 is necessary on such a stacked vertical gate structure.

摘要 I
Abstract III
致謝 V
目錄 VI
表目錄 VIII
圖目錄 IX
第一章 序論 1
1.1 快閃記憶體元件 1
1.1.1 浮動閘極式快閃記憶體元件 1
1.1.2 電荷捕陷式快閃記憶體元件 2
1.2 多晶矽薄膜電晶體 4
1.3 多向式閘極結構與奈米線通道式快閃記憶體元件 4
1.4 高介電係數材料與能帶工程之介紹 5
1.4.1高介電係數材料 5
1.4.2能帶工程 6
1.5 無接面快閃記憶體元件介紹 7
1.6 三維結構可堆疊式NAND快閃記憶體 9
1.7 各章摘要 10
第二章 快閃記憶體元件製程與操作方法 18
2.1快閃記憶體元件製程 18
2.1.1 傳統平面式快閃記憶體元件 18
2.1.2 奈米線式通道快閃記憶體元件製程 19
2.2 快閃記憶體元件寫入與抹除方法 20
2.2.1 CHEI通道熱電子注入寫入 20
2.2.2 F-N穿隧寫入 21
2.2.3 F-N穿隧抹除 22
2.3 快閃記憶體元件可靠度特性 22
2.3.1 電荷保持力 22
2.3.2 耐久力 23
2.4閘極與汲極之干擾特性 24
第三章 利用低溫成長二氧化矽的電荷穿隧層於多晶矽奈米線快閃記憶體元件特性研究 37
3.1研究動機與背景 38
3.2實驗 39
3.3結果與討論 40
3.3.1元件汲極電流對閘極電壓圖與成分分析 40
3.3.2元件寫入與抹除特性 40
3.3.3元件可靠度特性 41
3.4結論 42
第四章 利用低溫成長二氧化矽的電荷穿隧層於無接面式多晶矽奈米線快閃記憶體元件特性研究 57
4.1 研究動機與背景 58
4.2實驗 59
4.3結果與討論 59
4.3.1 元件汲極電流對閘極電壓作圖 59
4.3.2 元件寫入與抹除特性 60
4.3.3 元件可靠度特性 61
4.4 結論 62
第五章 利用低溫成長二氧化矽的電荷穿隧層於垂直閘極快閃記憶體元件特性研究 70
5.1研究動機與背景 70
5.2實驗 71
5.3結果與討論 72
5.3.1元件汲極電流對閘極電壓圖與成分分析 73
5.3.2元件寫入與抹除特性 73
5.3.3 元件可靠度特性 74
5.4結論 75
第六章 結論 87
參考文獻 89

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