本論文的研究以ALD的水氣電漿做為沉積介面層的主要製程，以得到高品質的GeO2及良好電特性為研究主軸，並進一步微縮EOT。探討沉積後退火熱處理的影響及介面層的溫度效應以及氮處理觀察元件電容電特性。最後以氮處理最佳特性製成電晶體元件研究其電特性。
熱處理方面使用氧氣沉積後退火製程能填補氧空缺，改善元件可靠度特性，達到0.9 nm之EOT，同時漏電低達10-3A/cm2，氧氣退火處理雖微增厚了EOT，但在多方面電特性上如介面陷阱密度(Dit)與可靠度上仍有優秀表現。
接著由於EOT的厚度與以往不同，首先改變了介電層物理厚度發現前驅物更換使得High-k不易結晶後，使用金屬沉積後退火處理(PMA)，進一步提高結晶性，使得High-k與介面層間達成良好混合，達到0.48 nm之EOT，同時漏電維持在10-1 A/cm2，物性上輔以TEM佐證，在遲滯、可靠度的量測上也看到金屬沉積後退火能改善元件特性。
接著則是使用不同介面層沉積溫度，發現以中溫250oC成長出之介面層與介電層之間有最好的混合效應，達到0.48 nm之EOT，並以平帶電壓值與遲滯表現上可以發現高溫370oC與低溫150oC之High-k內將有較多缺陷，導致平帶電壓增加，使得遲滯與可靠度有較嚴重之劣化，則250oC為介面層最佳成長參數。另一方面，也搭配使用不同介面層氮處理製程與實驗室從前之氫氣處理製程作比較，得到介面層之氮處理可以降低Dit，但也將使得EOT些微增加，氫氣處理可以提升High-k品質，但介面層缺陷將較多，而氮氣處理可以降低介面陷阱密度，卻會使得High-k內的缺陷較多，使得平帶電壓位移量增多，二種氣體處理各有其優點，取其優點應用。
最後則是延伸以往最佳參數製備Ge PMOSFET。其中，介面層之氫氣處理可以改善閘極控制電流能力，使得元件Gm有效提升，而介面層之氮氣處理將改善閘極關閉電流，壓低S.S.特性，將二者搭配使用先使用氮氣做介面處理在使用氫氣提升High-k特性，達成同時元件Gm高達3559 μA/V，並將S.S.下壓到238 mV/dec。另一方面，其載子遷移率可以高達401 cm2/V-s，反轉電容Tinv可仍然維持在0.57 nm，對應EOT則達到0.47 nm。因此認為介面層之氮氣處理與氫氣處理的先後搭配為最佳製程情況。

To further scale down equivalent oxide thickness (EOT) and get good electrical properties, a high quality Ge oxide interfacial layer (IL) is one of the key challenges for Ge MOS devices. A GeO2 formed by H2O plasma deposition in an ALD is used as a main IL in this thesis. Different processes are studied for Ge MOS devices, which includes post deposition annealing (PDA), different IL growth temperature, and in-situ nitrogen treatment. The best conditions are implemented on Ge MOSFETs fabrication.
The PDA is performed by a rapid thermal oxidation (RTO), which can passivate oxygen vacancy and provide better reliability. A Ge MOS device with 0.9 nm EOT and low leakage current of 10-3 A/cm2 is present. Although the EOT has slightly increased, the RTO sample shows good electrical properties such as low interface trap density (Dit) and good reliability.
It is found that EOT is quite different compared to the previous work. Some methods are provided to find the problems. The first way is changing the physical thickness of high-k dielectric layer. It found that it is difficult to crystallize high-k dielectrics and the k value of interfacial layer is quite low. Use the post metal deposition annealing can enhance the crystallization and enhance the intermixing between high-k and interfacial layer. As a result, 0.48 nm EOT and 10-1 A/cm2 leakage current is achieved. At the same time, hysteresis and reliability are improved as well. The results can be confirmed by TEM images.
Growth temperature is modified to obtain the best interfacial layer properties. The higher (370oC) and lower (150oC) growth temperature exhibit larger flat band voltage and hysteresis. These properties show that there are more traps in high-k dielectrics, leading to serious reliability degradation. The 250oC growth temperature shows 0.48 nm EOT, and it is the best condition for interface layer growth. On the other hand, in-situ nitrogen treatments in interfacial layer have been used. In-situ nitrogen treatment can suppress Dit but increase EOT and some traps in high-k dielectrics. Hydrogen treatment can enhance the quality of high-k but increase some traps in interfacial layer. Both treatments have their own advantages. The work in the next chapter will attempt to combine these two in-situ treatments.
At last, Ge MOSFETs are fabricated with the best condition from previous works. The hydrogen treatment can provide better gate control characteristic and increase Gm as well. The nitrogen treatment can suppress off current and S.S. To obtain all advantages, these two treatments have been combined with Ge MOSFETs processes. As a result, the high Gm value of 3559 μA/V and low S.S. of 238 mV/dec are achieved. The peak hole mobility is 401 cm2/V-s with 0.47 nm EOT. The in-situ nitrogen treatment together with hydrogen treatment in interfacial layers is a promising approach for Ge MOSFET devices.

摘要 I
致謝 V
目錄 VI
表目錄 IX
圖目錄 X
第一章　緒論 1
1.1 前言 1
1.2 使用HIGH-K介電材料的原因 1
1.3 HIGH-K介電材料的選擇 2
1.4 純鍺基板作為載子通道 3
1.6 介電層前驅物之影響 4
1.7 沉積後退火的影響 5
1.8 微波退火的機制 5
1.7 介面層鍺氧化物的性質與脫附效應 6
1.8 氫氣處理的影響 7
1.9 氮化處理的機制與影響 7
1.10 論文架構 8
第二章　元件製程與量測 17
2.1 不同ALD製程形成GEO2介面層搭配氮氧化鉿作為高介電層之純鍺基板MOS電容元件製程流程 17
2.1.1 實驗前晶片清洗 17
2.1.2 以H2O plasma參數製程之GeO2介面層製程與閘極介電層成長 17
2.1.3 金屬閘電極的形成 18
2.1.5 接出金屬導線、燒結 18
2.2 不同ALD製程形成GEO2介面層搭配搭配氮氧化鉿作為高介電層之純鍺基板MOSFET電晶體元件製程流程 19
2.2.1 源極(Source)、汲極(Drain)、基極(Base)的形成 19
2.1.5 接出金屬導線、沉積鈍化層、燒結 19
2.3 電性量測 20
2.3.1 Ge MOS電容量測 20
2.2.2 Ge MOSFET金氧半電晶體的量測 23
2.3物性分析 24
2.3.1 X光繞射儀 24
2.3.2 X射線光電子能譜儀 25
2.3.3 穿透式電子顯微鏡 25
第三章　熱處理對鍺金氧半電容特性的影響 32
3.1 研究動機 32
3.2 製程與量測 33
3.2.1 製程條件 33
3.2.2 量測參數 34
3.3 實驗結果與討論 36
3.4 結論 40
第四章　金屬沉積前後之退火處理對鍺金氧半電容元件特性的影響 51
4.1 研究動機 52
4.2 製程與量測 52
4.2.1 製程條件 52
4.2.2 量測參數 54
4.3 實驗結果與討論 54
4.3.1 改變介電層厚度對Ge MOS元件之電性分析 54
4.3.2 不同沉積後退火處理對Ge MOS元件之電性分析 55
4.4 結論 59
第五章　介面層經不同成長溫度及氮氣處理對金氧半元件特性研究 72
5.1 研究動機 73
5.2.1 製程條件 74
5.2.2 量測參數 75
5.3 實驗結果與討論 76
5.3.1 改變ALD內介面層成長溫度Ge MOS元件之電性分析 76
5.3.2 不同介面層氮化處理對Ge MOS元件之電性分析 79
5.4 結論 81
第六章　介面層經氮氣處理對MOSFET元件特性研究 98
6.1 研究動機 98
6.2製程與量測 100
6.2.1製程條件 100
6.2.2 量測參數 101
6.3實驗結果與討論 101
6.4 結論 104
第七章結論與展望 115
7.1 結論 115
7.2 未來展望 118
參考資料 120

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