隨著摩爾定律的發展，短通道效應一直都是CMOS技術繼續往前的一大難題。在此研究中，我們提出了溝槽式無接面鰭式多晶矽場效電晶體的製程技術和電性量測探討，進一步改善短溝道效應帶來的影響。此溝槽式結構可以讓閘極更有效包覆通道進而增強閘極的控制能力。即使無接面式電晶體需要超薄通道厚度才能使元件達到完全空乏的條件來關閉，溝槽結構的製程技術也可以非常容易得到超薄通道。我們利用非等向性的乾式蝕刻方式來形成溝槽式超薄主動層溝槽結構，溝槽結構可以定義出超薄通道厚度並且控制閘極的長度。而且，在重摻雜形成的主動層區域可以更加有效的抑制短通道效應。
在過去，若我們想製作超薄通道的元件通常是直接沉積很薄的膜來形成多晶矽通道，但現在我們利用乾式蝕刻來形成超薄通道。溝槽技術所形成的超薄通道比直接沉積薄膜獲得比較大的晶粒尺寸和比較少的晶粒邊界。
在此篇研究中，此溝槽式無接面電晶體(trench JL-FET)具有優越的SS值111 mV dec-1和極佳的開關特性(ION/ IOFF>108)，實際上量測到的DIBL值甚至小到可以忽略。溝槽式無接面電晶體(trench JL-FET)能有效的減少DIBL效應和通道長度調變效應。此外，在高電壓的操作下（超過平帶電壓），溝槽式無接面電晶體(trench JL-FET)擁有非常低的寄生電阻，這是因為在通道外的區域能帶都已形成了堆積層，此現象非常適合未來研究發展上的應用。更重要的是，此溝槽式無接面電晶體(trench JL-FET)的製程非常容易，對於先進的系統芯片（SOC）、低消耗功率元件和3D堆疊結構的應用上是非常有利的。

With the development of Moore's Law, short channel effect (SCE) has been always a serious issue for CMOS technology. This study, we describe the fabrication of a trench junctionless poly-Si fin field-effect transistor (trench JL-FET) to further improve short channel effect. This trench JL Fin-FET enhances the gate control over its silicon channel. The trench JL Fin-FET can easily to form the ultra-thin channel thickness (TCH) and control the gate length (LG) by dry etching. And, having the heavily doping channel and source/drain (S/D) regions, the SCE in JL-FET can be suppressed. Even if JL-FET requires the ultra-thin channel thickness to lead to the fully-depletion condition that would make the JL-FET turns off, the trench structure can easily integrated into the JL-FET device.
In the past, if we want to manufacture ultra-thin channel usually directly depositing the thin-film as the poly-Si channel. And now we use the dry etching to form the ultra-thin channel in JL FETs and it could get larger grain size and less grain boundary than directly depositing the thin-film.
In this study of characteristics analysis, the trench JL-FET has superior SS value about 111 mV dec-1, high ION/IOFF ratio up to 108 and practically negligible DIBL value. Trench JL Fin-FET with gated raised source/drain relieves drain-induced barrier lowering (DIBL) effect and channel length modulation effect. In addition, at a high voltage operation (over flat-band voltage of JL device), trench JL Fin-FET with gated raised source/drain reveals a low parasitic S/D resistance due to the formation of an accumulation layer at S/D, which is suit for multi-gate-oxide applications. Importantly, this trench JL Fin-FET along with simple fabrication is highly favorable for advanced system-on-chip (SOC), low power consumption applications and three-dimensional (3-D) stacked ICs applications.

中 文 摘 要 i
Abstract iii
Contents v
Figure Captions vi
Chapter 1 1
Introduction 1
1-1 THE CHALLENGE OF THE MOORE’S LAW 1
1-2 INTRODUCTION OF JUNCTIONLESS DEVICE 3
1-3 MOTIVATION 11
Chapter 2 19
Junctionless Mechanism 19
2-1 SUPERIORITY OF JUNCTIONLESS TRANSISTOR 19
2-2 BASIC PRINCIPLE OF JUNCTIONLESS TRANSISTOR 20
2-3 SHORT CHANNEL EFFECT (SCE) IN JUNCTIONLESS TRANSISTOR 28
Chapter 3 30
Device Fabrication and Simulation 30
3-1 DEVICE FABRICATION PROCESS 30
3-2 DEVICE SIMULATION 32
Chapter 4 34
Results and Discussion 34
4-1 THE PHYSICAL CHARACTERISTICS ANALYSIS (AFM/SEM/TEM) 34
4-2 THE DEVICE CHARACTERISTICS ANALYSIS 38
4-3 DEVICE TEMPERATURE PERFORMANCE 45
Chapter 5 48
Conclusion 48
Reference 50

Chapter 1

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Chapter 2

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Chapter 3
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Chapter 4
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