本論文旨在使用現場可程式化閘陣列(Field-Programmable Gate Array, FPGA)驗證編碼調變系統之解碼效能，採用正規化最小值-總和演算法(Normalized Min Sum Algorithm, NMSA)搭配單一區塊之行式分層(Single Block Column-Layered)排程法，硬體實現低密度奇偶檢查碼(Low-density parity-check code, LDPC code)解碼器。單一區塊行式分層排程可適用於所有行權重(column weight)、列權重(row weight)皆為1的循環矩陣(circulant matrix)所建構出的類循環LDPC碼(Quasi-Cyclic LDPC, QC LDPC)校驗矩陣(Parity check matrix, PCM)，並可降低FPGA硬體資源使用量、提升控制器設計的彈性。為提升在FPGA的編解碼吞吐量，本論文將傳統型編解碼器加以改良，可提供兩個碼字(codeword)同時進行編解碼流程，可提高兩倍的驗證速度。使用單一區塊行式分層排程法，搭配文獻所提出之1的個數較少之升序型(Ascending)校驗矩陣實現疊代式解調變解碼系統(Iterative Demodulation and Decoding, IDD)，與傳統1的個數較多之亂序型(Out-of-order)校驗矩陣相比，在50次的疊代次數下可達到2.03倍的吞吐量-面積比值(Throughput-Area Ratio, TAR)。

This thesis aims to evaluate the decoding performance of coded modulation system using a field-programmable gate array (FPGA) and implement low-density parity-check (LDPC) decoder using normalized min-sum algorithm (NMSA) with single block column-layered schedule. Single block column-layered schedule is applicable to all quasi-cyclic LDPC (QC-LDPC) parity check matrix (PCM) which constructed by the circulant matrix that column weight and row weight are equal to one. Furthermore, this schedule can reduce the utilization of FPGA hardware resources, and increase the flexibility of controller design. In order to improve the throughput of encoding and decoding on the FPGA evaluation, the traditional codec has to be improved. In this thesis, we designed a new codec which can apply encoding and decoding between two codeword simultaneously, and increase the speed of evaluation doubly. Compared with the traditional parity check matrix that arranged in out-of-order, the parity check matrix that arranged in ascending order and the percentage of 1's in PCM are less than the traditional, implemented on iterative demodulation and decoding (IDD) system using the single block column layered schedule has achieved the throughput-area ratio (TAR) of 2.03 in the number of iterations of 50.

1 簡介. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 動機. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 論文架構. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 背景回顧. . . . . . . . . . . . . . . . . . . . . 4
2.1 快閃記憶體工作原理概述. . . . . . . . . . . . . . . . . . . . . 4
2.2 類循環低密度奇偶檢查碼概述. . . . . . . . . . . . . . . . . . . 8
2.3 編碼調變系統概述. . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 非疊代式解調變解碼系統. . . . . . . . . . . . . . . . . 19
2.3.2 疊代式解調變解碼系統. . . . . . . . . . . . . . . . . . . 21
2.3.3 本論文採用之校驗矩陣. . . . . . . . . . . . . . . . . . . 23
2.4 適用於IDD系統之LDPC解碼器排程比較. . . . . . . . . . . . . 26
3 編碼調變系統之硬體實現. . . . . . . . . . . . . . . . 29
3.1 單一區塊之Column-Layered排程法. . . . . . . . . . . . . . . . 29
3.2 解調變器硬體設計. . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.1 Non-IDD系統. . . . . . . . . . . . . . . . . . . . . . . . 32
3.2.2 IDD系統. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.3 分段式8-PAM解調變器硬體設計. . . . . . . . . . . . . 35
3.3 NMSA搭配單一區塊Column-Layered排程之解碼器硬體設計. . 37
3.3.1 Non-IDD系統. . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.2 IDD系統. . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.3.3 Channel LLR記憶體設計準則. . . . . . . . . . . . . . . 49
3.3.4 單一區塊Column-Layered排程法之控制器設計準則. . . 51
4 編解碼器與驗證平台之設計. . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1 高吞吐量編解碼器. . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 驗證平台與軟硬體協同設計. . . . . . . . . . . . . . . . . . . . 74
5 模擬結果與結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1 環境參數設定. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2 模擬結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.2.1 SNR vs. BER/FER . . . . . . . . . . . . . . . . . . . . . 83
5.2.2 RBER vs. BER/FER/UBER . . . . . . . . . . . . . . . 84
5.2.3 平均疊代次數. . . . . . . . . . . . . . . . . . . . . . . . 86
5.3 硬體實作結果. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3.1 ASIC電路合成結果. . . . . . . . . . . . . . . . . . . . . 88
5.3.2 FPGA電路繞線結果. . . . . . . . . . . . . . . . . . . . 91
5.4 結論. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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