在半導體製程持續的快速進展下，從移動式電子產品到穿戴式電子產品都追求著低功耗和高密度的方向。意指著記憶體元件勢必要往非揮發記憶體(Nonvolatile Memory, NVM)靠攏，但是目前主流的快閃記憶體(Flash Memory)面臨到操作電壓太高和製程微縮的問題。於是在新型非揮發記憶體中的電阻式記憶體有極大的潛力。
本篇論文改善先前提出的接觸點電阻式記憶體(Contact Resistive Random Access Memory, CRRAM)，在原先的做法是利用接觸窗大小控制蝕刻電阻保護氧化層(Resistor Protection Oxide, RPO)效率。但因蝕刻變異性過大，導致薄膜厚度不均勻，進而導致電性變異與良率過低。
為此發展出新型結構為回填型接觸點電阻式記憶體(Backfill Contact Resistive Random Access Memory, BCRRAM)，在蝕刻接觸窗時，會以過蝕刻的方式將電阻保護層結構清除，以利於厚度控制。接著用電漿化學氣相沉積(Plasma-enhanced chemical vapor deposition, PECVD)回填二氧化矽(SiO2)，達到良好的厚度控制，且可套用於其他世代製程上。此結構可以接受一百萬次循環設定與重置和85oC二千小時烘烤，仍顯示可靠的資料儲存。
最後因為回填型接觸點電阻式記憶體是單極性電阻式記憶體，在操作時有過度寫入(Over Programming)疑慮。為了穩定元件的操作，導入逐步增加脈衝寫入(Incremental-step-pulse programming, ISPP)，逐步增加電壓更完善的控制阻值轉換，以達到提高耐久度。在一百萬次操作中，高低阻態差皆大於50倍。

In recent years, VLSI technology develops rapidly. Portable and wearable electronics products demanding low power high density nonvolatile memory. Flash Memory, the mainstream NVM, faces high operating voltage and process scaling problems, so resistive random access memory shows great potential in advance NVM devices.
This study proposed methods to improve the developmental issues of Contact Resistive Random Access Memory (CRRAM).The original CRRAM is fabricated by controlling RRAM thickness and contact size. Due to instability of contact hole etching rate, RRAM film could be non-uniform and affect yield rate. Backfill Contact Resistive Random Access Memory (BCRRAM) is proposed to solve this problem. A thin RRAM film is deposited into each contact hole by PECVD, instead. The BCRRAM can endure 1000k cycles and 85oC 2000hr baking without data alternation. Through experiment, the device proves no reliability concerns.
BCRRAM is a unipolar RRAM. Over programming damage may occur during reset operation. Therefore, Incremental Step Pulse Programming (ISPP) is included to optimize SET/RESET cycles to improve BCRRAM endurance. The ratio of LRS/HRS is greater than 50X, with more than 1000k cycles.

內文目錄
摘要 i
Abstract ii
致謝 iii
內文目錄 iv
附圖目錄 vi
附表目錄 viii
第一章 序論 1
1.1 非揮發性記憶體發展 1
1.1.1 磁阻式記憶體 1
1.1.2 相變化記憶體 2
1.1.3 電阻式記憶體 2
1.2 論文大綱 3
第二章 電阻式記憶體研究回顧 9
2.1 電阻式記憶體阻值切換模型 9
2.2 初始化操作 10
2.3 阻值切換操作與極性特性 10
2.4 電阻式記憶體介紹 10
第三章 接觸點電阻式記憶體研究 22
3.1 製程流程與元件結構 22
3.2 量測環境介紹 23
3.3 元件電性操作 23
3.4 電阻式薄膜厚度探討 24
3.5 可靠度分析 25
3.6 逐步增加脈衝(Incremental Step Pulse Programming, ISPP) 26
3.6.1 應用於改善元件操作 26
3.6.2 可靠度改善 27
3.7 小結 27
第四章 總結 56
參考文獻 57

[1] G. Atwood, “Future Directions and Challenges for ETox Flash Memory Scaling”, Device and Materials Reliability, IEEE Transactions on, vol. 4, pp.301-305, 2004.
[2] H. P. Belgal, N. Righos, I. Kalastirsky, J. I. Peterson, R. Shiner', and N. Mielke, "A new reliability model for post-cycling charge retention of flash memories," Reliability Physics Symposium Proceedings, 2002. 40th Annual, pp.7,20, 2002
[3] K. Kim, J. H. Choi, J. Choi, and H.-S. Jeong, "The future prospect of nonvolatile memory," VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on, pp.88,94, 25-27 April 2005.
[4] J. S. Moodera, Lisa R. Kinder, Terrilyn M. Wong, and R. Meservey., “Large Magnetoresistance at Room Temperature in Ferromagnetic Thin Film Tunnel Junctions”, in Phys. Rev. Lett., pp.3273-3276, 1995.
[5] D. Halupka, S. Huda, W. Song, A. Sheikholeslami, K. Tsunoda, C. Yoshida, and M. Aoki, “Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS”, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pp.256-257, 7-11 Feb. 2010.
[6] N. D. Rizzo, D. Houssameddine, J. Janesky, R. Whig, F. B. Mancoff, M. L. Schneider, M. DeHerrera, J. J. Sun, K. Nagel, S. Deshpande, H.-J. Chia, S. M. Alam, T. Andre, S. Aggarwal, and J. M. Slaughter, “ A Fully Functional 64 Mb DDR3 ST-MRAM Built on 90 nm CMOS Technology”, Magnetics, IEEE Transactions on , vol.49, no.7, pp.4441,4446, July 2013

[7] S. Ding, Z. Song, and H. Chen, “A 512 bits Phase Change Memory Embedded IP based on 0.18-μm CMOS process”, Electric Information and Control Engineering (ICEICE), 2011 International Conference on, pp.16-19, 15-17 April 2011.
[8] G. F. Close, U. Frey, J. Morrish, R. Jordan, S. Lewis, T. Maffitt, M. Breitwisch, C. Hagleitner, C. Lam, and E. Eleftheriou, “A 512Mb phase-change memory (PCM) in 90nm CMOS achieving 2b/cell”, VLSI Circuits (VLSIC), 2011 Symposium on, pp.202-203, 15-17 June 2011.
[9] D. R. Lamb and P.C. Rundle, “non-filamentary switching action in thermally grown silicon dioxide films”, in Appl. Phys. Lett.18, pp.29, 1967.
[10] A. Beck, J. G. Bednorz, Ch. Gerber, C. Rossel, and D. Widmer, “Reproducible switching effect in thin oxide films for memory applications”, in Appl. Phys. Lett. 77, pp.139, 2000.
[11] S. Karg, G. I. Meijer, D. Widmer, R. Stutz, J. G. Bednorz, and Ch. Rettner, “Nanoscale Resistive Memory Device Using SrTiO3 Films”, Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE, pp.68-70, 26-30 Aug. 2007.
[12] Y.-C. Huang, H.-M. Lin, and H.-C. Cheng, “Superior resistive switching characteristics of Cu-TiO2 based RRAM cell”, Nanoelectronics Conference (INEC), 2013 IEEE 5th International, pp.236-239, 2-4 Jan. 2013.
[13] C. B. Lee, B. S. Kang, M. J. Lee, S. E. Ahn, G. Stefanovich, W. X. Xianyu,K. H. Kim, J. H. Hur, H. X. Yin, Y. Park, and I. K. Yoo, “Electromigration effect of Ni electrodes on the resistive switching characteristics of NiO thin films”, in Appl. Phys. Lett.91, pp.082104, 2007.
[14] B. Chen, Y. X. Deng , B. Gao, R. Liu, L. Ma, P. Huang, F. F. Zhang, L. F. Liu , X. Y. Liu, and J. F. Kang, “High performance multilevel data storage in TaTiN/HfOx/Pt based RRAM using bipolar and unipolar combined switching mode”, Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on, pp.1-3, 29 Oct.-1 Nov. 2012.
[15] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, and M.-J. Tsai, “Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM”, Electron Devices Meeting (IEDM), 2013 IEEE International, pp.1-4, 15-17 Dec. 2008.
[16] L. Zhang, R. Huang, M. Zhu, S. Qin, Y. Kuang, D. Gao, C. Shi, and Y. Wang, “Unipolar TaOx-Based Resistive Change Memory Realized With Electrode Engineering”, Electron Device Letters, vol.31, no.9, pp.966-968, 2010.
[17] M. Marinella, “The future of memory”, Aerospace Conference, 2013 IEEE, pp.1-11, 2-9 March 2013.
[18] U. Russo, D. Ielmini, C. Cagli, and A. L. Lacaita, “Self-Accelerated Thermal Dissolution Model for Reset Programming in Unipolar Resistive-Switching Memory (RRAM) Devices”, Electron Devices, IEEE Transactions on, vol.56, no.2, pp193-200, 2009.
[19] M. Fujimoto, H. Koyama, M. Konagai, Y. Hosoi, K. Ishihara, S. Ohnishi, and N. Awaya, “TiO2 anatase nanolayer on TiN thin film exhibiting high-speed bipolar resistive switching”, in Appl. Phys. Lett. 89, pp. 223509, 2006.
[20] S. Yu, B. Lee, and H.-S. Philip Wong, “Metal oxide resistive switching memory”, in Springer Series in Materials Science Volume 149, pp.303-335, 2012.
[21] J. W. Seo, S. J. Baik, S. J. Kang, Y. H. Hong, J. H. Yang, and K. S. Lim, “A ZnO cross-bar array resistive random access memory stacked with heterostructure diodes for eliminating the sneak current effect”, in Appl. Phys. Lett. 98, pp.233505, 2011.
[22] W. G. Bennett, N. C. Hooten, R. D. Schrimpf, E. Robert, A.Reed, M. H. Mendenhall, M. L. Alles, JinshunBi, E. X. Zhang, D. Linten, M. Jurzak, and A. Fantini, “Single- and Multiple-Event Induced Upsets in HfO2/Hf 1T1R RRAM”, Nuclear Science, IEEE Transactions on, vol.61, no.4 pp.1717-1725, 2014.
[23] Y. Y. Chen, M. Komura, R. Degraeve, B. Govoreanu, L. Goux, A. Fantini, N. Raghavan, S. Clima, L. Zhang, A. Belmonte, A. Redolfi, G S. Kar, G. Groeseneken, D. J. Wouters and M. Jurczak, “Improvement of data retention in HfO2/Hf 1T1R RRAM cell under low operating current”, Electron Devices Meeting (IEDM), 2013 IEEE International, pp.10.1.1-10.1.4, 2013.
[24] H. Liu, H. Lv, B. Yang, X. Xu, R. Liu, Q. Liu, S. Long, and M. Liu, “Uniformity Improvement in 1T1R RRAM With Gate Voltage Ramp Programming”, Electron Device Letters, IEEE, vol.35, no.12, pp.1224-1226, 2014.
[25] Y. T. Li, S. B. Long, H. B. Lv, Q. Liu, M. Wang, H. W. Xie, K. W. Zhang, X. Y. Yang, and M. Liu, “Novel Self-compliance Bipolar 1D1R Memory Device for High-density RRAM Application”, Memory Workshop (IMW), 2013 5th IEEE International, pp.184-187, 26-29 May 2013.
[26] F. F. Zhang, P. Huang, B. Chen, D. Yu, Y. H. Fu, L. Ma, B. Gao, L. F. Liu, X. Y. Liu, and J. F. Kang, “Rectifying Characteristics and Implementation of n-SilHf02 based Devices for IDIR-based Cross-Bar Memory Array”, Silicon Nanoelectronics Workshop (SNW), 2012 IEEE, pp.1-2, 10-11 June 2012.
[27] Y. Li, W. Chen, W. Lu, and R. Jha,“Impact of coupling capacitance on read operation of RRAM devices in 1D1R crossbar architectures”, Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on, pp.989-992, 3-6 Aug. 2014.
[28] C.-W. Hsu, I-T. Wang, C.-L. Lo, M.-C. Chiang, W.-Y. Jang, C.-H. Lin, and T.-H. Hou, “Self-Rectifying Bipolar TaOx/TiO2 RRAM with Superior Endurance over 1012 Cycles for 3D High-Density Storage-Class Memory”, VLSI Technology (VLSIT), 2013 Symposium on, pp.T166-T167, 2013.
[29] M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park , I.-G. Baek and I.-K. Yoo, “2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications”, Electron Devices Meeting, 2007. IEDM 2007. IEEE International, pp.771-774, 10-12 Dec. 2007.
[30] C.-L. Lo, M.-C. Chen, J.-J. Huang, and T.-H. Hou, “On the Potential of CRS, 1D1R, and 1S1R Crossbar RRAM for Storage-Class Memory”, VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on, pp.1-4, 22-24 Apr. 2013.
[31] J. Lee, J. Shin, D. Lee, W. Lee, S. Jung, M. Jo, J. Park, K. P. Biju, S. Kim, S. Park and H. Hwang, “Diode-less Nano-scale ZrOx/HfOx RRAM Device with Excellent Switching Uniformity and Reliability for High-density Cross-point Memory Applications”, Electron Devices Meeting (IEDM), 2010 IEEE International, pp.19.5.1-19.5.4, 2010.
[32] S. Ambrogio, S. Balatti, D. Ielmini, and D. C. Gilmer, “Analytical modelling and leakage optimization in complementary resistive switch (CRS) crossbar arrays”, Solid State Device Research Conference (ESSDERC), 2014 44th European, pp.242-245, 22-26 Sept. 2014.
[33] H.-T. Lue, T.-H. Hsu, S.-Y. Wang, E.-K. Lai, K.-Y. Hsieh, R. Liu, and C.-Y.z Lu, “study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash”, Reliability Physics Symposium, 2008. IRPS 2008. IEEE International, pp.693-694, 2008.
[34] K.-T. Park, M. Kang, S. Hwang, Y. Song, J. Lee, H. Joo, H.-S. Oh, J.-h. Kim, Y.-T. Lee, C. Kim, and W. Lee, “Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories”, VLSI Circuits, 2009 Symposium on, pp.24-25, 16-18 June 2009.