隨者半導體科技不斷演進，元件裡的漏電流越來越明顯。而當隨者元件運作一段時間，使得traps累積在氧化層並增加漏電流。也使得時依性介電崩潰變得越來越重要在現今的科技發展下。
本篇論文探討著有關閘極穿隧電流對於元件的影響及模型。為了簡化模擬，我們會用佛勒-諾德翰穿隧電流模型 (Fowler-Nordheim tunneling current model)為基礎和分析。而在這篇會假設四種穿隧電流為來簡化分析:閘極穿隧電流，閘極到汲極，閘極到源極以及閘極到通道的穿隧電流。而穿隧電流在電路上的模擬用混和(元件和電路)模擬工具。
混和模擬需要額外的資源及模擬，在現今大量電晶體的模擬並不實際。也因此，我們會需要一個簡化的模型。由簡化的電阻連接在閘極與源極以及閘極與汲極，並在第二部分希望找到簡化的電路模型來縮短模擬的時間在合理的準度下。然而，我們發現沒辦法利用這些簡化電阻來表現所提到的穿隧電流。變得需要更多的研究來建立簡化電路模型對時依姓介電崩潰模擬。

As the semiconductor technology continues to shrink, significant gate leakage current is observed, especially when the devices are under stress for a long time. In this situation, traps may accumulate in the oxide and increases the leakage current. As this time, the time dependent dielectric breakdown(TDDB) is becoming an important issue for technology development.
The goal of this thesis is to study the impact of gate tunneling current to circuit performance. For easy simulation, Fowler-Nordheim tunneling current model is applied. The 4 different locations of the tunneling current are studied: uniform across the entire gate oxide, gate to drain tunneling, gate to source tunneling and gate to channel tunneling. The impacts of theses tunneling current to circuit operation are extensively simulated using mixed level (device and circuit levels) simulation tool.
Mixed level simulations need extensive computation resources and may not be practical in circuit design with large number of transistors, thus a simplified model is sough for. It is a common practice to represent the gate tunneling current by a resistor connecting gate to source or gate to drain. The second part of the thesis tries to find such a simple transistor model to speed up simulation and with reasonable accuracy. However, it is found no such model possible with simple resistor. More researches are needed to construct the circuit level model for TDDB simulations.

摘要 I
Abstract II
誌謝 III
Contents V
List of Figures VIII
List of Tables XIV
Chapter 1 Introduction 1
1.1 Background 1
1.2 Tunneling Current And Models 2
1.3 Organization Of The Thesis 4
Chapter 2 Previous work 5
2.1 Cell Delay Model In TDDB 5
2.2 TDDB Monitoring Circuit 7
2.3 Summary 8
Chapter 3 Gate Tunneling Impacts To The Circuit 9
3.1 Uniform Gate Tunneling 10
3.1.1 DC Analysis 10
3.1.2 Transient Analysis 12
3.2 Drain Tunneling 16
3.2.1 DC Analysis 16
3.2.2 Transient Analysis 18
3.3 Source Tunneling 21
3.3.1 DC Analysis 22
3.3.2 Transient Analysis 23
3.4 Channel Tunneling 26
3.4.1 DC Analysis 26
3.4.2 Transient Analysis 28
3.5 Tunneling Magnitude Impacts 31
3.6 Power Analysis 34
3.7 Different Tunneling Comparisons 36
3.7.1 Comparisons Between Drain And Uniform Tunneling: 36
3.7.2 Comparisons Between Source And Uniform Tunneling: 38
3.7.3 Comparisons Between Source And Channel Tunneling: 39
3.8 Conclusions 40
Chapter 4 Tunneling model fitting with simple resistor 42
4.1 Four Tunneling Model Voltages fit with R model: 43
4.2 Uniform tunneling fitting with RGD or RGS model 46
4.2.1 RGD DC Analysis 46
4.2.2 RGD – Transient Analysis 48
4.2.3 RGS DC Analysis 53
4.2.4 RGS Transient Analysis 54
4.3 Drain Tunneling Fitting With R Models 58
4.3.1 RGD DC Analysis 58
4.3.2 RGD Transient Analysis 59
4.3.3 RGS DC Analysis 62
4.3.4 RGS Transient Analysis 63
4.4 Source Tunneling Fitting With R Models 66
4.4.1 Special RGD model fitting 66
4.4.2 RGD DC Analysis 68
4.4.3 RGD Transient Analysis 69
4.4.4 RGS DC Analysis 72
4.4.5 RGS Transient Analysis 74
4.5 Channel Tunneling Fitting With R Models 77
4.5.1 RGD DC Analysis 77
4.5.2 RGD Transient Analysis 78
4.5.3 RGS DC Analysis 81
4.5.4 RGS Transient Analysis 82
4.6 Delay And Power Tables 84
4.7 Conclusions 89
Chapter 5 Conclusions and future work 90
5.1 Conclusions 90
5.2 Future work 91
References 92

[1] M. Alam, B. Weir, J. Bude, P. Silverman, and A. Ghetti, “A computational model for oxide breakdown: theory and experiments,” Microelectronic Engineering, vol. 59, no. 1-4, pp. 137 – 147, 2001.

[2] A. Haggag, "Realistic Projections of Product Fails from NBTI and TDDB," Proc. 44th Ann. IEEE Int'l Reliability Physics Symp., pp. 541-544, 2006.

[3] J. S. né, G. Mura and E. Miranda, "Are soft breakdown and hard breakdown of ultrathin gate oxides actually different failure mechanisms? ," IEEE Electron Device Lett., vol. 21, no. 4, pp. 167-169, 2000.

[4] B. Kaczer, R. Degraeve, "Gate oxide breakdown in FET devices and circuits: from nanoscale physics to system-level reliability," Microelectronics Reliability, vol 47, pp. 559-566, May 2007.

[5] M. Choudhury, V. Chandra, K. Mohanram, and R. Aitken, “Analytical model for TDDB-based performance degradation in combinational logic,” Design, Automation & Test in Europe (DATE) Conference, pp. 423–428, March 2010.

[6] H. Nan and K. Choi,” TDDB Monitoring and Compensation Circuit Design for Deeply Scaled CMOS Technology,” Device and Materials Reliability, IEEE Transactions ,vol 13, no. 1, pp. 18-25 , 2013 .

[7] J. Sune and E.Y. Wu, "Statistic of successive breakdewn events in gate oxides,” IEEE Electron Device Lett., vol. 24, no. 4, pp. 272-274, 2003

[8] 90-nm-Device Topology and schematic:
http://www-mtl.mit.edu/researchgroups/Well/device1/topology1.html#references

[9] S. Sahhaf , R. Degraeve , P. J. Roussel , T. Kauerauf , B. Kaczer and G. Groeseneken, "TDDB reliability prediction based on the statistical analysis of hard breakdown including multiple soft breakdown and wear-out", Proc. IEDM Tech. Dig., pp. 501-504, 2007

[10] J. C. Ranuárez, M. J. Deen, , C. H. Chen ,“A Review Of Gate Tunneling Current In MOS Devices,” Microelectronics Reliability, Vol. 46, pp. 1939-1956, 2006.

[11] K. F. Schuegraf and C. Hu, “Metal-oxide-semiconductor field-effect-transistor substrate current during Fowler-Nordheim tunneling stress and silicon-dioxide reliability,” J. appl. Phys, vol. 76, no. 6, pp. 3695-3700 , sep 1994.

[12] A. Latreche, “An Accurate Method for Extracting the Three Fowler- Nordheim Tunnelling Parameters Using I-V Characteristic,” Microelectronics and Solid State Electronics, pp 59-64 ,2013.

[13] E. Miranda and J. Su˜n´e, "A Function-Fit Model for the Soft Breakdown Failure Mode," IEEE Electron Device Letters, vol. 20, no. 6, pp. 265-267, 1999.

[14] H. Luo, X. Chen, J. Velamala, Y. Wang, Y. Cao, V. Chandra, Y. Ma, H. Yang, "Circuit-level delay modeling considering both TDDB and NBTI," in 12th International Symposium on Quality Electronic Design (ISQED), pp.1, 2011.

[15] B. Kaczer, R. Degraeve, A. De Keersgieter, K. Van de Mieroop, V. Simons and G. Groeseneken," Consistent model for short-channel nMOSFET after hard gate oxide breakdown,” IEEE Transactions on Electron Devices, vol. 49, no. 3, pp. 507-513, 2002.

[16] L. Gerrer, G. Ghibaudo, “Oxide soft breakdown: from device modeling to small circuit simulation,” In: Proc ESSDERC, p. 355–8, 2009.

[17] A. F. Shulekin, S. É. Tyaginov, R. Khlil, A. El Hdiy, M. I. Vexler, “Soft Breakdown as a Cause of Current Drop in an MOS Tunnel Structure,” Physics of Semiconductor Devices, Vol. 38, p 724-726, Jun 2004.

[18] S. Y. Kim, C.-H. Ho and K. Roy, "Statistical SBD modeling and characterization and its impact on SRAM cells," IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 54-59, 2014.

[19] M.-Y. Tsai, H.-C. Lin, D.-Y. Lee and T.-Y. Huang, "Post-soft-breakdown characteristics of deep submicron NMOSFETs with ultrathin gate oxide," IEEE Electron Device Lett., vol. 22, no. 7, pp. 348-350, 2001.