本篇論文重點在於製作新型邊緣終結保護結構-反摻雜接面終結延伸的技術，藉由反向佈植Ⅴ族元素，將單區接面終結延伸內過多的載子排除，降低接面終結延伸的佈植劑量，形成像是多區域的接面終結延伸。藉由模擬不同種類的邊緣終結保護結構來證明反摻雜接面終結延伸比起其他的結構擁有非常寬廣的佈植劑量窗口。
本次實驗製作各種不同結構的邊緣終結保護結構於11μm與30μm的漂移區上，藉由佈植不同的接面終結延伸劑量來證明反摻雜接面終結延伸確實擁有寬廣的佈植劑量窗口並且崩潰電壓達90%理想值以上。
本次實驗量測30μm的漂移區上，反摻雜接面終結延伸結構在中佈植劑量與高佈植劑量的崩潰電壓可達4800V，約95 %的理想崩潰電壓。與模擬結果相互比對後可得知在熱退火1650℃ 10分鐘的情況下，活化率約為60 %。

In this work, a new edge termination technique for high-voltage devices in 4H-SiC, Counter-Doped-Junction Termination Extension (CD-JTE), is proposed, simulated, and fabricated. CD-JTE uses n-type implant incorporated in the p-type JTE region, which counter-dopes and reduces the effective JTE dose. A multiple zone effect can be realized without multiple implantations and masks. Numerical simulations have been performed for different edge terminations and compared with the new structure. CD-JTE exhibits a high breakdown capability with an improved tolerance in the deviation of JTE dose.
Diodes with different edge terminations are fabricated on 11μm and 30μm epi-wafers with different implantation doses to demonstrate the advantages of CD-JTE experimentally. The best breakdown voltage for 30μm diodes is 4800V (about 95% of the ideal value) for a device with CD-JTE termination and with medium dose and high dose JTE implantation. Compared with simulation results, implant activation rate is estimated to be about 60% for an annealing at 1650oC for 10 min.

目錄
中文摘要 I
Abstract II
第一章 序論 1
1.1 碳化矽材料簡介 1
1.2 功率元件的崩潰機制 2
1.2.1 簡介 2
1.2.2 累增崩潰 2
1.3 邊緣終結保護結構 4
1.4 文獻回顧 5
1.5 研究動機與論文大綱 6
第二章 元件設計與模擬 8
2.1 邊緣終結保護結構 8
2.2 邊緣終結保護結構設計與模擬 8
A. 接面終結延伸(JTE) 9
B. 接面終結延伸協助防護式環形結構(GAJ) 10
C. 接面終結延伸附加浮動式環形場(JTE+OR) 10
D. 接面終結延伸協助防護式環形結構附加浮動式環形場(GAJ+OR) 11
E. 反摻雜接面終結延伸(CD-JTE) 12
F. 反摻雜接面終結延伸附加浮動式環形場(CD-JTE+OR) 13
2.3 邊緣終結保護結構比較 14
第三章 製程實驗 28
3.1 一般清潔(Normal Clean) 28
3.2 對準記號(Alignment key) 29
3.3 陽極離子佈植(Main Junction Implant) 29
3.4 接面終結延伸離子佈植 30
3.5 反摻雜佈植(Counter-Doped Implant) 31
3.6 電性活化(Electrical activation) 32
3.7 保護層(Passivation) 32
3.8 陽極歐姆接觸(Anode Ohmic Contact) 33
3.9 陰極歐姆接觸(Cathode Ohmic Contact) 33
第四章 實驗結果分析與討論 41
4.1 順向偏壓特性(Forward Characteristics) 41
4.2 逆向偏壓特性(Reverse Characteristics) 42
4.2.1 11μm磊晶層 43
4.2.2 30 μm磊晶層 46
4.3 發光量測分析 49
第五章 結論與未來展望 79
參考文獻 80

 

參考文獻

[1]A. R. Powell and L. M. Ghezzo, “SiC Material-Progress Status and Potential Roadblocks, ” IEEE Proc., vol. 60, pp.942-955,2002.
[2] G. R. Fisher and P. Barnes, “Toward a unified view of polytypism in silicon carbide,” Phil. Mag. B, vol. 61, no. 2, pp. 217–236, Feb. 1990.
[3] H. Matsunami and T. Kimoto, “Step-controlled epitaxial growth of SiC:High quality homoepitaxy,” Mater. Sci. Eng., vol. 20, no. 3, pp. 125–166, Aug. 1997.
[4] M. Bhatnagar and B. J. Baliga, “Comparison of 6H-SiC, 3C-SiC, and Si for power devices,” IEEE Trans. Electron Devices, vol. 40, no. 3, pp. 645–655, Mar. 1993.
[5]B. J. Baliga, Power Semiconductor Devices. Boston, MA: PWS Publ. Co., 1995, pp. 81-123.
[6]D.C. Sheridan and J.N. Merrett, “Design and Characterization of 2.5kV 4H-SiC JBS Rectifiers with Self-Aligned Guard Ring Termination,” Mater. Sci. Forμm, vol. 353-356, pp. 687-690, 2001
[7] W. Bahng. and G. H. Song, “Fabrication and Characterization of 4H-SiC pn Diode with Field Limiting Ring,” Mater. Sci. Forμm, vol. 457-460, pp. 1013-1016, 2004
[8] Marc C. Tarplee, Vipin P. Madangarli, and Quinchun Zhang, “Design Rules for Field Plate Edge Termination in SiC Schottky Diodes,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2659-2664, Dec. 2001.
[9] E. A. Imhoff, and F. J. Kub, “High-Performance smoothly tapered junction terminaion extensions for high-voltage,” IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3395-3400, Oct. 2011.
[10] Woongje Sung, and Edward Van Brunt, “A New Edge Termination Technique for High-Voltage Devices in 4H-SiC–Multiple-Floating-Zone Junction Termination Extension,” IEEE Trans. Electron Devices, vol. 32, no. 7, pp. 880-882, July. 2011.
[11] Koji Nakayama. and Ryosuke lshii, “Component Technologies for Ultra-High-Voltage 4H-SiC pin Diode,” Mater. Sci. Forμm, vol. 679-680, pp. 535-538, 2011
[12] V. Veliadis. and M. Snook, “Process Tolerant Single Photolithography/Implantation 120-Zone Junction Termination Extension,” Mater. Sci. Forμm, vol. 740-742, pp. 855-858, 2013
[13] Lei Lin, and Jian H. Zhao, “Simulation and experimental study of 3-step junction termination extension for high-voltage 4H-SiC gate turn-off thyristors,” Solid State Electron., vol. 86, pp. 36-40, April. 2013.
[14] R. Pérez. and N. Mestres, “A highly effective edge termination design for SiC planar high power devices,” Mater. Sci. Forμm, vol. 457-460, pp. 1253-1256, 2004
[15] Kozo Kinoshita. and Tetsuo Hatakeyama, “Guard Ring Assisted RESURF: A New Termination Structure Providing Stable and High Breakdown Voltage for Sic Power Devices,” IEEE Power Semiconductor Devices and ICs, pp. 253-256, 2002.
[16]Toru Hiyoshi, and Tsutomu Hori, “Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes,” IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 1841–1846, August. 2008.
[17] Hiroki Niwa, and Gan Feng, “Breakdown Characteristics of 12-20 kV-class 4H-SiC PiN Diodes with Improved Junction Termination Structures,” International Symposiμm on Power Semiconductor Devices and ICs, pp. 381-384, June. 2012.
[18] F. Giannazzo, and F. Roccaforte, "Acceptor, compensation, and mobility profiles in multiple Al implanted 4H SiC," Appl. Phys. Express, vol.91 , pp. 202104-1-202104-3, 2007.
[19]Y.Negoro, K. Katsμmoto, T. Kimoto, and H. matsunami, “Electronic behaviors of high-dose phosphorus-ion implanted 4H-SiC(0001),”Journal of Applied Physics, vol. 96, pp. 224-228 no. 1, 2004.
[20] T. Hatakeyama, and J. Nishio, “Physical Modeling and Scaling Properties of 4H-SiC Power Devices,” Simulation of Semiconductor Processes and Devices, pp. 171–174, Sept. 2005.
[21] A. O. Konstantinov, and Q. Wahab, “Ionization Rates and Critical Fields in 4H SiC Junction Devices,” Mater. Sci. Forμm, vol. 264-268, pp. 513-516, 1998