近年來，由於無線通訊技術的蓬勃發展，進入了高速資料傳輸通訊系統的時代，對目前而言無線網路技術的發展使得ISM頻段已產生擁擠與不敷使用的情況，必須將電路設計的操作頻率向上提升，進而達到傳送更大量資料的需求，例如微波和毫米波頻段。本論文的目標是完成應用於衛星通訊系統的高增益、低雜訊RF接收機設計，其頻段為Ku-band (10.7 - 13.45GHz)。
本論文提出兩個使用0.18μm SiGe製程設計的射頻接收機前端電路以及一個使用90nm CMOS製程設計的頻率合成器，接收機前端電路的Mixer使用電流注入式架構提升線性度，中頻放大器使用多重回授和3D電感增加頻寬與線性度，兩個接收機前端電路的不同在於LNA架構，其中一個使用變壓器回授技巧達成阻抗匹配同時也有低雜訊的表現，另一顆則用共閘極做輸入匹配並使用CCC技術，讓阻抗匹配容易設計。兩顆射頻前端電路的增益有45 dB以上，皆有達成設計目標。
頻率合成器以低相位雜訊為設計目標，參考頻率為50 MHz，迴路頻寬是500 kHz以及相位邊限為66°，為了能使除頻器能操作於較高的頻率而使用動態E-TSPC電路來減少延遲，除數範圍是從128到255。VCO是用Class-F型來增加zero-crossing點的斜率以減少相位雜訊，頻率合成器的相位雜訊在1 MHz offset處為-121 dBc/Hz，相位雜訊明顯改善。

In recent years, the ISM bands have become crowded due to the increasing popularity of various wireless communication applications. One possible solution is to move from the low GHz range towards higher operating frequencies such as microwave and millimeter-wave bands to have wider bandwidths and higher data rate. This thesis focuses on the design of high-gain, low-noise RF receiver front-end for satellite communication systems. The target operating band is from 10.7GHz to 13.45GHz (Ku-band).
This thesis proposes two RF receiver front-ends fabricated in 0.18μm SiGe and a frequency synthesizer fabricated in 90nm CMOS. The mixer of receiver front-end uses the current bleeding structure to improve linearity and the IF amplifier uses multiple feedback and 3D inductor to increase bandwidth and linearity. The main of the two receiver front-ends different is the low-noise amplifier. One design uses the transformer feedback technique to accomplish impedance matching and low noise. The other uses the common-gate structure and CCC technique for improved wideband-matching. The gains of both receiver front-ends are above 45 dB, which meet the design target.
The synthesizer focuses on low-phase noise. The reference frequency is 50 MHz. The loop bandwidth is 500 kHz and the phase margin is 66°. The divider uses dynamic E-TSPC circuit to reduce delay for operating higher frequency. The divide ratio is from 128 to 255. The VCO in synthesizer uses Class-F type to increase zero-crossings slope for reducing phase noise. The phase noise of synthesizer at 1 MHz offset is -121 dBc/Hz. It is improved apparently.

致謝 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
表目錄 x
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 3
Chapter 2 Basic Concepts of RF Receiver 4
2.1 Basics of Low Noise Amplifier Design 4
2.2 Basics of Mixer Design 8
2.3 Nonlinearity 12
2.4 Summary 14
Chapter 3 High-Gain Receiver Front-end for Ku-Band Applications 15
3.1 Design of High-Gain Receiver - Design I 15
3.1.1 LNA using transformer feedback technique 15
3.1.2 Current Bleeding Mixer 19
3.1.3 IF Amplifier with 3D Inductor 21
3.1.4 Simulation and Measurement Results 27
3.2 Design of High-Gain Receiver - Design II 31
3.2.1 CCC-LNA with Transformer Matching 31
3.2.2 Simulation and Measurement Results 35
3.3 Summary and Comparison 39
Chapter 4 Basic Concepts of Frequency Synthesizer 40
4.1 Basics of Phase-Locked Loop 40
4.2 Phase Noise 45
4.3 Summary 46
Chapter 5 Low-Phase Noise Synthesizer for Ku-Band Applications 47
5.1 Design of Low-Phase Noise Synthesizer 47
5.1.1 Phase Frequency Detector and Charge Pump 47
5.1.2 Loop Filter 49
5.1.3 Divider Chain 50
5.1.4 Class-F VCO 51
5.1.5 Simulation Results 54
5.2 Summary and Comparison 56
Chapter 6 Conclusion and Future Work 57
References 58

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