SRAM(靜態隨機存取記憶體)是一種廣泛被用在作為處理器暫存器、高速緩存器及各式各樣的緩衝器中的揮發性記憶體。雖然一旦斷電所儲存的資料就會消失，但由於它極快的讀取/寫入速度及趨近無限的耐寫/耐讀性，使得SRAM 在記憶體的領域中佔有主導的地位。由於SRAM 的主要架構是兩交叉藕合反相器的純邏輯電路，因此它也常被整合在同樣是邏輯電路的處理器晶片上以減低晶片之間封裝的成本。
隨著半導體製程技術的推進，邏輯電路中電晶體的臨界電壓值勢必要隨著電源電壓而下降，期望可以達到更快的操作頻率及更省電的效果。然而，因為製程技術的微縮及追求更小的面積，使得半導體的製造變得更加困難，在摻雜或以光罩定義位置時將會有更大的變動性，製作過程所產生的元件特性變異將會更加嚴重。若無法減低這些製程變異所造成的影響，將會在使用時發生資料錯誤。
本論文提出一種結合邏輯相容一次性寫入記憶體的新型靜態隨機存取記憶體，利用該記憶體的自我收斂及在SRAM 架構下特有的操作機制，使得製程變異的影響可以在不需要改變製作過程的情況下被適當的減低。因此，這個新型的SRAM 可以有更好的靜態雜訊邊限，並有效的減少讀取錯誤的機會。

SRAM (Static Random Access Memory) is a dominating at type
of volatile memory, widely used in CPU registers, CPU caches, and various kinds of buffers with the characteristics of fast read/write
access time and infinite read/write endurance. Because SRAM is a pure
logic circuitry composed of cross-coupled inverters, it is embedded in
logic CMOS process to further reduce the cost in packaging.
As process technology scales, threshold voltage of the transistors
in SRAM cells must decreases for the need of supply voltage scaling
while variation of threshold voltage increases as a result of dopant
fluctuation and size fluctuation in minimization of critical dimensions.
These fluctuations must be minimized or some soft errors might
happen to cause read/write mistakes when operates.
In this work, we introduce a new logic compatible OTP
(One-Time Programmable) Memory made up of SAN (Self-Aligned
Nitride) structure to combine with SRAM cells. Through blanket
programming operation and self-convergent characteristics of the OTP
cell, process variations can be effectively suppressed in the new SRAM
to improve SNM (Static-Noise Margin). The read failure rate due to
static noise can be reduced. Therefore, the variation caused by process
can be solved by blanket trimming operations.

內文目錄
摘要 i
Abstract ii
致謝 iii
內文目錄 iv
附圖目錄 vii
附表目錄 ix
第一章 序論 1
1.1 揮發性記憶體介紹 2
1.2 SRAM設計在製程微縮下的挑戰 2
1.3 論文大綱 3
第二章 SRAM的基本操作及近年來減少製程變異影響的方法 8
2.1 靜態雜訊邊限(Static Noise Margin, SNM) 8
2.1.1 空閒時的SRAM 8
2.1.2 讀取時的SRAM 9
2.1.3 寫入時的SRAM 9
2.2 臨界電壓變異值對靜態雜訊邊限的影響 9
2.3 近年來用以減低製程變異對SRAM影響的方法 10
2.3.1 讀取路徑的改變 10
2.3.2 製程上的改變 10
2.3.3 直接減少SRAM中電晶體的臨界電壓變異值 11
2.4 小結 11
第三章 結合邏輯相容一次性寫入記憶體之新型靜態隨機存取記憶體 22
3.1 自我對準氮化矽一次性寫入記憶體之介紹 22
3.1.1 元件架構 23
3.1.2 製作過程 23
3.2 元件電性操作 24
3.2.1 寫入機制 24
3.2.2 讀取特性 24
3.2.3 元件電性量測 25
3.3 結合自我對準氮化矽一次性寫入記憶體之新型 靜態隨機存取記憶體 26
3.4 小結 26
第四章 新型靜態隨機存取記憶體量測特性 37
4.1 讀取電流的不匹配特性 37
4.2 新型SRAM臨界電壓值調整機制 38
4.2.1 Blanket Trimming Operation 38
4.2.2 不同操作電壓下的VT調整操作 39
4.3 資料儲存性 39
4.4 VT調整操作之後的分佈比較 40
4.5 臨界電壓調整操作對SNM的影響 40
4.6 小結 41
第五章 總結 49
參考文獻 51

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