近年來，隨著CMOS-MEMS製程的進步，微機電麥克風取代了傳統駐極體式麥克風成為主流，應用於不同的消費性電子產品上。由於微機電麥克風的電容變化相當微小，因此需要低雜訊的讀出電路將訊號放大並讀出。
本論文於0.25μm BCD製程下設計一接面場效電晶體(JFET)元件當作讀出電路的輸入緩衝器，並與低雜訊放大器整合在一起，相較於MOSFET，JFET有著較低的閃爍雜訊。藉由JFET低雜訊的特性，將閃爍雜訊最小化，改善傳統上使用大面積MOSFET降低閃爍雜訊而造成感測器訊號衰減的問題。
為驗證JFET之可行性，設計另一組以MOSFET作為輸入緩衝器的對照組做比較。由量測結果證實，採用JFET版本之架構，可降低閃爍雜訊，相比於MOSFET版本之架構有較小的輸入相關雜訊。

In recent years, with the progress of CMOS-MEMS technology, MEMS microphone gradually replaced the traditional Electret Condenser Microphone (ECM) and became the mainstream in consumer electronic products. Due to the small capacitance change single from MEMS microphone is quite small, a low noise readout circuit is needed to amplify the signal.
Conventionally, the MOSFET with large size was used to reduce flicker noise, but it also caused the degradation of sensor signal. JFET has lower flicker noise than MOSFET so we designed a JFET as the input buffer for readout circuit to solve the problem and integrated the low noise amplifier with it. This IC was fabricated with TSMC 0.25μm BCD process.
In order to verify the feasibility, we designed another circuit in which the JFET input buffer was replaced by a MOSFET as control group of samples. Confirmed by the measurement results, using JFET in the amplifier can reduce flicker noise, and compared to the MOSFET version obtain lower input referred noise.

第一章 緒論 10
1.1 研究動機 10
1.2 相關研究發展 3
1.3 論文章節架構 5
第二章 MEMS麥克風之讀出電路特性 6
2.1 MEMS Microphone 操作原理 6
2.2 MEMS Microphone 前端放大器架構 8
2.3 雜訊源分析 10
2.3.1 熱雜訊 10
2.4 接面場效應電晶體操作原理 13
2.5 常見雜訊抑制放大器 15
2.5.1相關雙取樣(Correlated Double Sampling) 15
2.5.2 截波穩定(Chopper Stabilization) 18
2.5.3 架構比較 20
第三章 電路設計 22
3.1 整體架構簡介 22
3.2 JFET元件架構 22
JFET量測結果 23
3.3 輸入緩衝器(Input buffer) 25
3.4 儀表放大器(Instrumentation Amplifier) 26
3.4.1 Operational Amplifier 27
3.4.2 Constant gm偏壓電路 29
3.5 正電壓電荷泵(Positive voltage charge pump) 30
3.6負電壓電荷泵(Negative voltage charge pump) 31
3.7 產生延遲時脈控制(Non-overlapping clock generation circuit) 32
第四章 模擬結果 33
4.1 輸入緩衝器 33
4.2 運算放大器 35
4.3 前端放大器 36
4.4正電壓電荷泵 39
4.5負電壓電荷泵 40
第五章 晶片佈局與量測 42
5.1 晶片佈局 42
5.1.1 JFET 佈局 42
5.1.2 晶片佈局 44
5.2 PCB板設計 47
5.3 量測與討論 48
5.3.1 量測設備與環境 48
5.3.2 量測結果 50
5.3.3 量測結果討論 58
第六章 總結 60
6.1 結論 60
6.2後續研究 60
參考文獻 61

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