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作者(中文):秦永文
論文名稱(中文):三維雙位元通孔電阻式隨機存取記憶體研究
論文名稱(外文):A study of 3D Twin-bit Via RRAM by 28nm Cu Backend Process
指導教授(中文):林崇榮
口試委員(中文):高明哲
金雅琴
林崇榮
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電子工程研究所
學號:101063532
出版年(民國):103
畢業學年度:102
語文別:中文
論文頁數:72
中文關鍵詞:電阻式隨機存取記憶體自我整流電阻式記憶體陣列連通管原理
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近幾年,智慧型手機、平板電腦等可攜式電子產品快速發展普及,3C對小體積大容量的儲存裝置需求日漸增加。快閃記憶體(Flash Memory)是目前市場中眾多非揮發性記憶體的主流,然而隨著製程微縮,Flash memory即將面臨到其物理極限,這也加速了許多新型記憶體的研究,其中最被看好的下一世代記憶體為電阻式隨機存取記憶體。
本篇論文提出一種新型雙位元通孔電阻式隨機存取記憶體(Twin-bit Via Resistive Random Access Memory, Twin-bit Via RRAM),此記憶體通孔兩邊皆有氧化物薄膜,因此單一元件即擁有雙位元儲存。此論文中的研究元件是製作於銅製程雙鑲嵌結構,採用28奈米High-k metal gate互補式金氧半導體邏輯製程,此元件優點為低阻態擁有自我整流特性、極大的高低阻態比、轉換速度快、完全相容於互補式金氧半導體邏輯製程以及優異之可靠度特性。
由於三維快閃記憶體陣列的成功,為了與之競爭,電阻式記憶體勢必也要能堆疊成三維陣列。因為雙位元通孔電阻式記憶體的自我整流特性,在堆疊三維陣列時無需加入額外的整流器;在設計的操作電壓下,此元件陣列通過了10k次設置/重置干擾;此陣列是完全建構在後端製程,周邊電路可以放在陣列的正下方,進一步節省面積。本篇論文提出的雙位元通孔電阻式記憶體及其陣列,有機會成為下一世代記憶體陣列的解決方案之一。
摘要 i
Abstract ii
致謝 iii
內文目錄 iv
附圖目錄 vi
附表目錄 viii
第一章 導論 1
1.1 非揮發性記憶體現況 1
1.2 論文大綱 2
第二章 電阻式隨機存取記憶體文獻回顧 3
2.1 電阻式隨機存取記憶體介紹 3
2.1.1 電阻式記憶體技術回顧 3
2.1.2 初始化 4
2.1.3 設置/重置與操作極性 4
2.1.4 電阻式隨機存取記憶體模型 5
2.2 電阻式記憶體陣列相關研究 6
2.2.1 連通管原理及金氧半電晶體驅動陣列 6
2.2.2 互補式電阻式記憶體陣列 7
2.2.3 二極體驅動電阻式記憶體陣列 7
2.3 小結 8
第三章 三維雙位元通孔電阻式隨機存取記憶體 22
3.1 元件結構與製程 22
3.2 量測環境介紹 23
3.3 元件操作與元件特性 23
3.3.1 元件操作特性分析 23
3.3.2 元件讀取電流特性 24
3.4 元件可靠度分析 25
3.4.1 連續讀取干擾測試 25
3.4.2 資料保存性 25
3.4.3 元件變異分析 26
3.5 小結 26
第四章 三維雙位元通孔電阻式隨機存取記憶體陣列 47
4.1 二維陣列操作及特性分析 47
4.1.1 二維陣列操作 47
4.1.2 寫入干擾測試 48
4.1.3 不同二維陣列佈局及特性比較 48
4.2 交錯式字元線設計與三維陣列 49
4.3 梳子狀三維陣列 50
4.4 小結 51
第五章 總結 67
參考文獻 68
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