本論文的目標是利用自我對準P井及源極傾斜角度離子佈植來製作出短通道的4H碳化矽垂直型雙佈植金氧半場效電晶體。並配合歐姆金屬自我對準製程，來縮小元件的單位線寬，因而達到降低特徵導通電阻的期望。
本次實驗根據上述製程製作出D-mode DMOSFET元件，量測到最佳特徵導通電阻為57.95 mΩ*cm2，此時量測條件為閘極電壓20伏特、汲極電壓1伏特，發生在較小動作區面積31482 um2及較長有效通道寬度5004 um、JFET長度4 μm的元件。另外本次實驗量測到的最佳崩潰電壓是在磊晶層厚度為30 μm的sample僅700伏特，應該是由於P井離子佈植在1650oC退火的活化不完全，導致在反向高壓時的橫向擊穿。

The goal of this thesis is to use self-aligned p-well and n-source ion implantation with tilting an angle to fabricate a short channel 4H-SiC double implant MOSFET. Also with a self-aligned ohmic contact process, the device cell pitch can be shrunk and hence the specific on resistance is expected to reduce significantly.
In this experiment, we have demonstrated D-mode DMOSFETs with the proposed process and the best RON,SP is 57.95 mΩ*cm2, extracted when Vg = 20 V and Vd = 1 V on a device with a smaller active area of 31482 um2, a longer effective channel width of 5004 um and a JFET length of 4 μm. The best breakdown voltage measured in this work is only 700 V on a sample with a epi-layer thickness of 30 μm. And the possible explanation is the incomplete p-well ion implantation activation at 1650oC anneal, which causes lateral punch-through at high reverse biases.

中文摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VIII
第一章 序論 1
1.1 介紹碳化矽材料 1
1.2 垂直型雙佈植金氧半電晶體 (Vertical Double Implant MOSFET) 2
1.3 文獻回顧 3
1.4 研究動機與論文大綱 5
第二章 元件設計與模擬 6
2 DMOSFET元件改善 6
2.1 通道電阻改善 6
2.1.1 自我對準製程 (Self-Aligned Process) 6
2.1.2 氧化熱退火製程 7
2.2 JFET區域電阻改善 7
2.3 歐姆接觸金屬自我對準製程 8
2.4 邊緣終結保護結構 (Edge Termination) 8
2.5 離子佈植阻障層 9
2.6 DMOSFET元件模擬 10
第三章 製程實驗 17
3.1 一般清潔 (Normal Clean) 17
3.2 P井離子佈植 (P-well Implant) 17
3.3 源極離子佈植 (Source Implant) 18
3.4 基極離子佈植 (Body Implant) 19
3.5 接面終端延伸離子佈植 (Junction Termination Extension Implant) 19
3.6 反摻雜離子佈植 (Counter-Doped Implant) 20
3.7 閘極氧化層成長 (Gate Oxide Formation) 21
3.8 閘極電極定義 (Gate Electrode Definition) 21
3.9 源極與基極歐姆接觸 (Source & Body Ohmic Contact) 22
3.10 汲極歐姆接觸與快速熱退火 (Drain Ohmic Contact & Rapid Thermal Annealing) 23
3.11 閘極電極窗口打開與源極墊金屬 (Gate Electrode Window Opening & Source Pad Metal) 23
第四章 實驗量測分析與探討 33
4.1 測試元件 33
4.2 DMOSFET元件 34
第五章 結論與未來展望 49
參考文獻 50

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