由於科技的進步，大眾對於高速資料傳輸的需求逐漸提高。使用有線介面傳輸，訊號會受到傳輸介質的影響，使原先的訊號受到衰減。將傳輸介質替換成光纖，可提供高頻寬且低雜訊的優點，因此近年來短距離光纖通訊系統在資料傳輸上扮演很重要的角色。
光通接收器在整合上會遇到一些問題，其中最大的挑戰為電路頻寬的限制，若要有較大的光電流輸出勢必要加大光感測器(Photo Diode, PD)的面積大小，故PD的寄生電容也會隨之加大，將直接影響到接收器的頻寬。
本論文利用TSMC 0.18m CMOS製程下實現10Gb/s光通接收器之無被動電感前端放大器的設計，在PD的寄生電容為1pF下，整合了轉阻放大器(Transimpedance Amplifier, TIA)以及限幅放大器(Limiting Amplifier, LA)。在此次設計的電路中使用電壓-電流回授、主動電感以及主動回授電路來拓寬頻寬，並使用內部主動回授來使極點分離，此一方法可以使頻譜平坦化。本次設計亦將差動主動米勒電容(Differential Active Miller capacitor, DMAC)來取代外接式電容，有效減小晶片面積且可避免晶片外部雜訊的干擾。

Due to the progress in technology, high-speed data transmission is highly demanded. In the traditional wire communication, the signal suffers high loss from transmission medium as the data-rate increases. However, replacing the traditional transmission medium by optical fiber provide the advantage of wide bandwidth and low noise. Therefore, short-distance optical communication plays a major role in high-speed data transmission.
Among the problems about fully integration of optical receiver on a single chip, one of the difficult challenges is the limit of bandwidth due to the size of photodetector. To increase photocurrent makes the size of the photodiode (PD) larger. However, the parasitic capacitance of the PD will become larger and directly affect the bandwidth of the whole optical receiver.
This thesis proposes an inductorless front-end amplifier, fabricated in TSMC 0.18 m CMOS technology, for 10 Gb/s optical receiver under the condition of 1 pF parasitic capacitance of the PD. The chip integrates a transimpedance amplifier (TIA) and a limiting amplifier (LA). By employing shunt-shunt feedback, active inductor, and active feedback, this work broadens the bandwidth. Besides, the interleaving feedback in the circuit not only splits the poles but also make the frequency response flat. Conventional off-chip capacitors are replaced by differential active Miller capacitors (DAMC) in this work in order to achieve an area-efficient design and to avoid off-chip noise.

第一章 序論 1
1.1研究背景與發展與現況 1
1.2研究動機 4
1.3論文章節架構 6
第二章 光接收器系統參數 7
2.1增益(Gain) 7
2.2頻寬(Bandwidth) 8
2.3上升時間(Rise Time)、下降時間(Fall Time) 9
2.4眼圖(Eye Diagram) 9
2.5誤碼率(Bit Error Rate) 10
2.6靈敏度(Sensitivity) 11
2.7抖動(Jitter)[1, 3-6] 11
2.7.1隨機抖動(Random Jitter, RJ) 13
2.7.2定量性抖動(Deterministic Jitter, DJ) 13
2.7.3眼圖範例 15
2.8單極非回零式碼(Unipolar Non-Return to Zero, NRZ) 16
第三章 光接收器之電路設計 18
3.1光接收器系統介紹 18
3.2設計流程 19
3.3光接收器系統規格 20
3.4轉阻放大器(Transimpedance Amplifier, TIA)架構 21
3.4.1 Regulated Cascade with Shunt-Shunt Feedback 21
3.4.2 Balun 24
3.5準位自動控制 (Auto DC Control)電路 27
3.5.1準位自動控制 (Auto DC Control)電路 27
3.5.2差動型主動式米勒電容 28
3.6限幅放大器(Limiting Amplifier, LA) 29
3.6.1後級放大器架構比較 29
3.6.2限幅放大器增益級 31
3.6.3疊接影響 32
3.6.4限幅放大器設計 35
3.7直流偏移消除電路(DC Offset Cancellation) 35
3.8輸出級(Output Stage or Slicer) 36
3.9固定轉導偏壓電路(Constant Gm bias circuit) 37

第四章 光接收器系統模擬 39
4.1製程Corner變異(TT/FF/SS)模擬結果(Post simulation) 39
4.1.1 TT之下的Post simulation 39
4.1.2 FF之下的Post simulation 42
4.1.3 SS之下的Post simulation 44
4.2電壓變異考量 47
4.2.1電壓上升10%( VDD=1.98V)之下的Post simulation 47
4.2.2電壓下降10%( VDD=1.62V)之下的Post simulation 49
4.3溫度變異考量 52
第五章 量測結果與討論 53
5.1晶片佈局考量 53
5.2 PCB板設計 55
5.3量測環境及儀器介紹 57
5.4量測結果 59
5.5量測結果探討 63
5.6文獻比較 73
第六章 結論與後續建議 75
6.1結論 75
6.2後續建議事項 75
參考文獻 76

 

[1]B. Razavi, Design of Integrated Circuits for Optical Communication Systems, America: McGraw-Hill, 2003.
[2]E. Sackinger, Broadband Circuits for Optical Fiber Communication, America: John Wiley & Sons Inc., 2005.
[3]劉秉澄，應用於10Gb/s之高效能矽鍺限幅放大器設計，碩士論文，清華大學，新竹，2007。
[4]http://www.agilent.com, Jitter Analysis Techniques for High Data Rates,Application Note 1432
[5]http://www.agilent.com,安捷倫數位量測研習營系列¬¬¬-抖動與信號完整量測篇。
[6]http://www.eetimes.com/document.asp?doc_id=1277196
[7]Simon Haykin, Communication Systems, 5th Edition, John Wiley & Sons, 2010.
[8]L.Chen, Z.Li , and Z. Wang, “A 10-Gb/s 0.18-um CMOS optical receiver front end amplifier,” Proc. Asia-Pacific Conf. on Comm., pp. 601-604, 2009
[9]S. M. Park, and H. J. Yoo, “1.25-Gb/s regulated cascade CMOS
transimpedance amplifier for gigabit Ethernet applications”, IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 112-121, Jan. 2004.
[10]H.Y. Huang, J.C. Chien, and L.H.Lu, “A 10-Gb/s inductorless CMOS limiting amplifier with third-order interleaving active feedback,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1111–1120, May 2007.
[11]Chen, Lili, et al. "A 10-Gb/s CMOS differential transimpedance amplifier for parallel optical receiver," Signals Systems and Electronics (ISSSE), 2010 International Symposium on. Vol. 1. IEEE, 2010.
[12] Z. H. Lu, K. S. Yeo, W. M. Lim, M. A. Do and C. C. Boon,"Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.461-472 (2010).
[13]M. Atef and H. Zimmermann, “10Gb/s inductorless transimpedance amplifier,” in Proc. IEEE ISCAS, 2012, pp. 1728–1731.
[14]Xiao-Xia Wang, Zhi-Gong Wang,Ji-Shun Liu,Ｘue-Mei Lei, “10-Gb/s High- Density Trns-Impedance Amplifier in 0.18-um CMOS,”IEEE Wireless Communication & Signal Processing, Nov. 2009
[15]廖偉傑，標準製成下應用於整合型光通接收器之光偵測器元件與訊號放大電路設計，碩士論文，清華大學，新竹，2011。
[16]R. Ludwig and P. Bretchko, RF Circuit Design Theory and Applications, New Jersey: Prentice Hall, 2000.
[17] Stephen H. Hall, Garrett W. Hall, James A. McCall (2000), High-Speed Digital System Design—A Handbook of Interconnect Theory and Design Practices, New York: John Wiley & Sons.
[18]S.-H. Huang, W.-Z. Chen, Y.-W. Chang, and Y.-T. Huang, “A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 46, no. 5, pp.1158–1169, May 2011
[19]W. Z. Chen, Y. L. Cheng, and D. S. Lin, “A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end,” IEEE J. Solid-StateCircuits, vol. 40, no. 6, pp. 1388–1396, Jun. 2005
[20]W.-Z. Chen and S.-H. Huang, “A 2.5 Gbps CMOS Fully Integrated Optical Receiver with Lateral PIN Detector,” Proceedings of Custom Integrated Circuits Conference, San Jose, 16-19 September 2007, pp. 293-296.