本論文主要運用電荷汲引法來探討碳化矽溝槽式閘極電晶體不同晶向的介面缺陷密度和通道電子遷移率的關係。關鍵的基極採用磊晶技術來達到所需摻雜濃度並減少離子佈植時產生的損傷，溝槽式閘極電晶體製作在碳化矽的主要晶面上並用深溝槽作為隔離製程。
本研究採用三種介電層，結果顯示通道電子遷移率及閾值電壓和晶向無關聯性，可能如文獻中所提及一氧化碳(NO)退火的影響。60分鐘NO氧化加氧化鋁沉積的電子遷移率為24 cm2/V*s，20分鐘NO氧化加氧化鋁沉積的電子遷移率為18 cm2/V*s，乾氧氧化加NO退火的電子遷移率為10 cm2/V*s。
60分鐘NO氧化加氧化鋁沉積的平均介面缺陷密度為1.2*1012 eV-1-cm 2，在其它表面得到相近的值，結論是NO退火將產生氮化介面層，抑制各向異性的特性與文獻一致。

This thesis mainly focuses on the study of anisotropic channel mobility of trench-gate MOSFET SiC on different crystal orientations using charge pumping technique to correlate interface trap density and channel mobility. The critical p-body was formed by epitaxy for the target doping concentration and reduction of implantation damages. Trench-gate MOSFETs were fabricated on major SiC orientations and isolated with deep trenches.
Three different gate dielectrics were employed in this study. The results show little dependence of channel mobility and threshold voltage on orientation, possibly due to NO anneal as reported in the literature. The channel mobility is 24 cm2/V*s with 60 minutes NO oxidation plus aluminum oxide deposition, 18 cm2/V*s with 20 minutes NO oxidation plus aluminum oxide, and 10 cm2/V*s with dry oxidation plus NO annealing.
The average interface state density of 60 minutes NO oxidation plus aluminum oxide is 1.2*1012 eV-1-cm 2, extracted by charge pumping. Similar numbers were obtained on other surfaces. It is concluded that the NO anneal process will introduce a nitride interface layer and suppress anisotropic characteristics, which is consistent with literature.

中文摘要 I
Abstract I
目錄 II
圖目錄 V
表目錄 X
第一章 序論 1
1.1 寬能隙材料 4H-碳化矽 (4H-SiC) 1
1.2 碳化矽晶格結構 2
1.3 溝槽式閘極金氧半電晶體 2
1.4 文獻回顧 3
1.5 研究動機與論文大綱 4
第二章 元件設計 8
2. Trench-Gate MOSFET元件設計 8
2.1 原子層化學氣相沉積 8
2.2 介電層改善 9
2.3 電荷汲引量測(Charge pumping measurement) 10
2.3.1 電荷汲引操作及原理 11
2.3.2 電荷汲引量測裝置 12
第三章 製程實驗 18
3.1 一般清潔(Normal cleaning) 18
3.2 對準鍵(Alignment key)和基極區域蝕刻(Body etching) 18
3.3 基極離子佈植(Body implantation) 19
3.4 電性活化(Electrical activation) 19
3.5 溝槽蝕刻(Trench etching) 19
3.6 犧牲氧化層(Sacrificial oxide) 20
3.7 閘極氧化層1(Gate dielectric 1) 20
3.8 汲極歐姆接觸(Drain ohmic contact) 20
3.9 源極歐姆接觸(Source ohmic contact) 21
3.10 基極歐姆接觸(Body ohmic contact) 21
3.11 快速熱退火(Rapid thermal annealing) 21
3.12 閘極氧化層2(Gate dielectric 2) 21
3.13 閘極金屬接觸(Gate metal contact) 22
第四章 實驗量測結果與討論 26
4.1 電容及UMOSFET特性量測 26
4.2 電荷汲引電流量測 27
4.3 變溫特性量測 29
4.4 加壓量測(Stress) 30
第五章 結論與未來展望 57
參考文獻 58

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