隨著高速資料時代的來臨，無線通訊系統必須往更高頻帶發展，才能傳輸如此爆炸性成長的資料量。毫米波(30~300 GHz)的頻段裡，此區擁有足夠的頻寬因此非常適合傳輸數個或數十個Gbps的資料。本文主要研究使用互補式金氧半導體(CMOS)製程技術實現在V頻帶(57~64 GHz)和W頻帶(75~110 GHz)之系統與區塊電路設計。
於V頻段應用中，本論文完成一個使用TSMC 90-nm CMOS製程之無參考時脈的光通轉射頻傳輸機。此電路中提出使用載波回復技術，直接萃取資料的時脈並且倍頻至60 GHz以達到系統整合的目的。因此系統在實際應用裡不需要額外的晶體振盪器作為參考時脈源也可以將資料調變發送出去。於此傳輸機中，本地振盪源之調整範圍約為5 GHz，相位雜訊約為-87 dBc/Hz在1 MHz偏移量處。射頻端部分，此傳輸機約有5 dBm的最大輸出功率和14 GHz的頻寬，可將2.5 Gb/s的資料使用BPSK調變發射。此系統總功率消耗為256 mW，操作電壓為1.2 V。
於W頻段應用中，本論文完成使用TSMC 90-nm CMOS製程完成一79 GHz的壓控振盪器、80 GHz OOK解調接收機和105 GHz的頻率除法器。在79 GHz壓控振盪器中，本論文提出一三重變壓器調整技術，解決高頻下可變電容品質因數惡劣的問題。並且為了確保在高頻下滿足起振條件，本電路結合了雙重疊接式交錯對技術提高共振腔在高頻時的阻抗負實部。此壓控振盪器約有5.6 GHz的調整範圍，其相位雜訊約為-107.7 dBc/Hz在10 MHz偏移量處。核心電路功率消耗為7.3~25.8 mW，操作電壓為1.2 V。
在80 GHz OOK解調接收機中，改良傳統波封檢測器頻寬不足的問題，提出使用Cherry-Hooper回授之檢測器並且加入電感性負載增加頻寬。本論文提出一可解調資料最快到12.5 Gb/s的波封檢測器，中心頻為80 GHz。線性度部分，IP1dB約為-16 dBm。輸出眼圖抖動約為8.7% UI。總功率消耗為67.5 mW，操作電壓為1.2 V。
在105 GHz頻率除法器中，本論文提出為一除五的注入鎖定式除頻器，使用變壓器共振腔技術減輕輸出緩衝級的等效電容負載。並且加入感性共振技術降低注入對受寄生效應而增益不足的問題。其在105 GHz可以提供約4 GHz的鎖定範圍。核心電路功率消耗為5.7 mW，操作電壓為1 V。

With the coming of the era of high-speed data, wireless communication systems must operate at increased frequency bands to transmit such explosively growing data. The millimeter wave frequency range (30~300 GHz) has a sufficient bandwidth which is very suitable for GHz and tens-of-Gbps applications. In this thesis, we mainly focus on realizing building blocks for phase-locked loop and transceiver front-end in V-band (57~64 GHz) and W-band (75~110 GHz) with CMOS technology.
In V-band, we have introduced a reference-less optical-RF interface transmitter (TX) in TSMC 90-nm CMOS technology. We propose “carrier recovery” technique to extract the clock of data directly. The signal is then multiplied to 60 GHz for system integration. Therefore, in real applications, there is no need for using a crystal oscillator as the reference clock, and the system can still transmit the data. The tuning-range of the proposed carrier is about 5 GHz and the phase noise is about -87 dBc/Hz at 1-MHz offset. The TX provides a maximum output power of 5 dBm with a bandwidth of 14 GHz. The maximum transmitted data rate is 2.5 Gb/s with BPSK modulation. The total power consumption of the system is 256 mW with a 1.2 V supply voltage.
We have also realized a 79 GHz voltage-controlled oscillator (VCO), an 80 GHz OOK demodulation receiver (RX), and a 105 GHz frequency divider in TSMC 90-nm CMOS technology, all in the range of W-band. For the 79 GHz VCO, we introduce a “trifilar tuning” technique to overcome the poor quality factor of the varactors at high frequencies. Besides, we combine another technique called “double-stacked cross-coupled pair” to enhance the negative resistance of tank at high frequencies in order to ensure oscillation. The VCO provides about 5.6 GHz tuning-range with a phase noise of -107.7 dBc/Hz at 10 MHz offset. The core power consumption is about 7.3~25.6 mW with a 1.2 V supply voltage.
For the 80 GHz OOK demodulation RX, we improve the insufficient bandwidth of the conventional envelope detector, and propose a Cherry-Hooper based envelope detector with inductive peaking to enhance the operation bandwidth. We have realized an envelope detector operating at 12.5 Gb/s, at central frequency of 80 GHz. The IP1dB of the RX is about -16 dBm. The output peak-to-peak jitter is about 8.7% UI. The total power consumption of the system is 67.5 mW with a 1.2 V supply voltage.
For the 105 GHz frequency divider, a divide-by-5 injection-locked frequency divider (ILFD) with a transformer tank was proposed to reduce the effective capacitive loading from the output buffers. Moreover, another inductor is added to resonate with the parasitic capacitances of the injectors and solves the problem of insufficient gain. The divider provides about 4 GHz locking-range at central frequency of 105 GHz. The core power consumption is about 5.7 mW with a 1 V supply voltage.

ACKNOWLEDGEMENT i
ABSTRACT ii
摘要 iv
CONTENTS vi
LIST OF FIGURES ix
LIST OF TABLES xiv
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 2
CHAPTER 2 A 60 GHZ REFERENCE-LESS BPSK TRANSMITTER 3
2.1 High-speed Wireless Data Links 3
2.2 Radio-over-fiber and Baseband-over-fiber 4
2.3 Clock and Data Recovery Loop 6
2.3.1 Phase Detector 6
2.3.2 Frequency Detector 8
2.4 A 60 GHz Reference-less BPSK Transmitter 9
2.4.1 Introduction 9
2.4.2 Carrier Recovery Technique 11
2.4.2.1 Clock Recovery Circuit 11
2.4.2.2 Voltage-Controlled Oscillator 14
2.4.2.3 Frequency Divider Chain 15
2.4.2.4 CML Multiplexer 16
2.4.3 BPSK Modulator 17
2.4.4 Proposed System Topology 17
2.4.5 Simulated Results 19
2.5 Summary and Comparison 22
CHAPTER 3 A 79 GHZ LOW PHASE NOISE AND WIDE TUNING-RANGE VCO 24
3.1 Basics of Oscillators 24
3.2 Phase Noise of an Oscillator 26
3.2.1 Leeson’s Model (LTI model) 27
3.2.2 Hajimiri’s Model (LTV model) 30
3.3 A 79 GHz Low Phase Noise and Wide Tuning-Range VCO 33
3.3.1 Introduction 33
3.3.2 Analysis and Design of Trifilar 36
3.3.3 Analysis and Design of DSCCP 37
3.3.4 Proposed Circuit 40
3.3.5 Simulated and Measured Results 42
3.4 Summary and Comparison 44
CHAPTER 4 AN 80 GHZ OOK DEMODULATION RECEIVER 46
4.1 Basics of Digital Modulation 46
4.1.1 Signal Constellations 46
4.1.2 Quadrature Modulation 47
4.2 OOK Transceiver Architecture 48
4.3 An 80 GHz OOK Demodulation Receiver 49
4.3.1 Introduction 49
4.3.2 Analysis and Design of the 80 GHz LNA 50
4.3.3 Analysis and Design of the Envelope Detector 51
4.3.4 Analysis and Design of the Limiting Amplifier 52
4.3.5 Proposed System Topology 54
4.3.6 Simulated Results 56
4.4 Summary and Comparison 59
CHAPTER 5 A 100 GHZ DIVIDE-BY-5 ILFD 62
5.1 Basics of RF Frequency Dividers 62
5.1.1 True-Single-Phase Clocking (TSPC) 62
5.1.2 Current-Mode Logic (CML) 63
5.1.3 Miller Divider 64
5.1.4 Injection-Locked Frequency Divider (ILFD) 65
5.2 Locking-Range of ILFD (Razavi’s Model) 66
5.3 A 100 GHz Dvide-by-5 ILFD 69
5.3.1 Introduction 69
5.3.2 Analysis of Divide-by-5 ILFD 71
5.3.3 Analysis and Design of the Transformer Tank 72
5.3.4 Analysis and Design of the Shunt Peaking Inductor 75
5.3.5 Proposed Circuit 77
5.4 Summary and Comparison 80
CHAPTER 6 CONCLUSIONS AND FUTURE WORKS 82
6.1 Conclusions 82
6.2 Future Works 83
REFERENCE 84

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