隨著資料傳輸與處理量日益增加，為了解決傳統金屬導線所造成的非理想效應，越來越多研究著手在光連結系統上。在此篇論文中，我們著重在設計超高速光通訊的前端電路。前三章在介紹使用標準CMOS製程所設計的光通訊收發機，第四章則是選擇了SiGe HBT來達到更快速的接收機前端電路，最後一章將作出一個結論。
第二章裡，運用電感增加頻寬的40 Gb/s 轉阻放大器被實作於標準90 nm CMOS製程中，在1.5 V的供應電壓下此電路只消耗10.5mW，在25 Gb/s的運作速度下可以有52dBΩ的轉阻增益，由於此電路中的電感皆是使用三維螺旋形電感，所以有極小的晶片面積0.4*0.45 〖mm〗^2跟核心面積0.024 〖mm〗^2。
第三章裡，40 Gb/s的調變器驅動電路被實作於標準40 nm CMOS 製程中，此電路的主要目的是要跟University of Southampton Optoelectronics Research Center所提供的調變器做結合。在負載50歐姆的狀況下，此調變器區董電路在12.5Gb/s與25Gb/s的速度中可達到1.66 V_PP 與1.4 V_PP，而在供應電壓維2/4V的情形下此電路消耗功率為337 mW，而核心電路僅佔0.012 〖mm〗^2。
第四章裡，100+ GHz 的轉阻放大器被實作於 0.13 μm SiGe，此製成是由Innovations for High Performance Microelectronics 或 IHP所提供，此電路的3-Db頻寬可達到110 GHz而且在3.3V的供應電壓下只消耗功率22.8mW，此電路擁有50 dBΩ的轉阻增益，晶片面積只有170*500 〖mm〗^2並且核心面積只要30*50 〖mm〗^2。

With the data volume of transmission and processing getting larger and larger, in order to solve the non-ideal effects of conventional metal lines, more and more researches put efforts on optical interconnects. In this thesis, we focus on designing ultra-high speed front-end circuits of optical communications. The first three chapters show the design and implement of optical transceiver in standard CMOS technology. In chapter four, we use the SiGe HBT technology to achieve a faster receiver front-end circuit. Finally, a conclusion is given in chapter five.
In chapter 2, a 40-Gb/s transimpedance amplifier with an inductor peaking technique in 90 nm CMOS has been implemented. The power consumption of the TIA without output buffer was about 10.5 mW under a supply voltage 1.5 V. The TIA reached a transimpedance gain of 52 dBΩ with an operation speed of 25 Gb/s. The chip area is 0.4*0.45 〖um〗^2 including four 3D solenoid inductors with a core area of only 0.024 〖mm〗^2. The measurement results show this design is suitable for 25 Gb/s operation.
In chapter 3, a compact 40 Gb/s inductorless modulator driver is proposed and implemented in 40 nm CMOS for the purpose of integration with the silicon-based high speed modulator, provided by University of Southampton Optoelectronics Research Center. Under the termination of 50Ω, the modulator driver can reach 1.66 V_PP and 1.4 V_PP at the data speed of 12.5 Gb/s and 25 Gb/s. The power consumption is 337 mW under the supply voltage 2/4 V and the core area is only 0.012 〖mm〗^2.
In chapter 4, a 100+ Gb/s inductorless transimpedance amplifier is proposed and implemented in 0.13-μm SiGe, provided by Innovations for High Performance Microelectronics (IHP). The simulated results show a 3-dB bandwidth can achieve 110 GHz while only consuming 22.8 mW under a supply voltage of 3.3 V. The transimpedance gain is 50 dBΩ and the chip area is 170*500 〖um〗^2 with the core area of only 30*50 〖um〗^2. The eye-diagram at the speed of 100 Gb/s shows well opened in the simulation results.

CONTENTS
ABSTRACT i
摘要 iii
CONTENTS iv
LIST OF FIGURES vi
Chapter1 Introduction 1
1.1 Background and motivation 1
Chapter2 40-Gb/s transimpedance amplifier with reverse triple resonance network 3
2.1 Introduction of transimpedance amplifier 3
2.2 Peaking skills 5
2.2.1 Shunt peaking inductor 5
2.2.2 T-coil peaking 6
2.2.3 Π peaking 7
2.3 Proposed RTRN TIA 8
2.3.1 Reversed Triple Resonance Network 9
2.3.2 3D inductor 10
2.3.3 Second Stage and Output Buffer 15
2.4 Simulation and measurement results 16
Chapter3 Design of 40-Gb/s Modulator Driver in 40 nm CMOS 22
3.1 Introductions of modulator driver 22
3.2 Design consideration of modulator driver 23
3.3 Output Impedance Matching and Output Stage 24
3.4 Proposed Two-Stage Modulator Driver 27
3.4.1 Second Order Active Feedback 28
3.4.2 Cascode Output Stage with Transistor Protection 30
3.5 Simulations and Measurement Results 33
Chapter4 100+GHz transimpedance amplifier 38
4.1 Introduction of 100 GHz TIA 38
4.2 Proposed 100 GHz TIA 38
4.2.1 RGC 39
4.2.2 fT doubler 41
4.3 Simulation and measurement results 43
Chapter5 Conclusion 48
REFERENCES 50

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