矽電晶體的發明帶來了電子行業的巨大成功，為了得到更多的電路密度和低功率操作，晶體體的尺寸以按比例縮小。然而，驅動電晶體的電源電壓(VDD)並未按電晶體密度比例縮小，其根本原因在於MOSFET臨界電壓 (VTH)的和次臨限擺幅（Subthreshold Swing, S）的限制。因MOSFET被次臨限擺幅的限制，才需要不同的承載機構來改變陡次臨限擺幅的限制。更陡次臨限擺幅允許較低的電源電壓(VDD)和低功率操作，因為電力尺度是電源電壓(VDD)的平方。具有更陡次臨限擺幅的元件表現較低的柵極電壓（Gate Voltage）和展現更高的開關電流比例(ION/IOFF)。所以當今技術的主流是更高的ON電流、低的OFF電流和較低的電源電壓。
為了克服MOSFET的次臨限擺幅（S）限制，需要具有不同的載流子注入機制的新開關元件。在這項實驗中，探索了穿隧場效電晶體（TFET）作為替代開關裝置，以克服CMOS中的次臨限擺幅（S）的基本限制。穿隧場效電晶體（TFET）以帶對帶穿透效應(BTBT)的方式將載流子注入，並具有無熱（kT）的依賴，這允許次臨限擺幅（S）更陡峭和其值小於60 mV/dec。
除了新元件和載流子注入機制外，本實驗採用低帶隙材料（Low Bandgap Material），鍺(Ge)作為源區的材料，主要為了大大提高ON電流和ON/OFF 比例。除了鍺源區材料外，本實驗採用閘極重疊結構(Gate Overlap Structures)以改變穿隧方式（由點變線穿隧）來得到從元極到通道的更多穿隧道區(Tunneling Area)。在這項實驗中，為了提高帶對帶穿透效應(BTBT)、ON電流和ON/OFF 比例，應用了不同條件的實驗：3～5 nm的閘極氧化層（Gate Oxide）厚度、10～20 nm的間隔（Spacer）厚度、15～45 sccm的摻雜流量（Doping Flows）、1E15～5E15 cm-2 的摻雜濃度（Doping Concentrations）。
本實驗中量測到的ID-VG或計算到的次臨限擺幅（S）值，可以結論說，閘極氧化層越薄或間隔厚度越薄或摻雜流量越高會得到更高的ON電流、更陡峭的次臨限擺幅。隨著更高的汲極電壓（VD），量測到的ON電流也會更高。對有和無閘極重疊結構而言，有閘極重疊結構的次臨限擺幅值小於60 mV/dec，但無極重疊結構的次臨限擺幅值大於60 mV/dec。對ON電流而言，有閘極重疊結構比無閘極重疊結構多2個orders的電流且它們的ON/OFF比例為2個orders。

ABSTRACT

The invention of Silicon transistor brings the electronic industry to the great success. In order to get more circuit density and operate at low power, the dimension of transistors goes to be scaled down. However, the supply voltage (VDD) used to drive the transistors has not proportionately scaled down with transistor density. The root cause is that the scaling down in VDD is attributed to the non-scalability of the MOSFET threshold voltage (VTH) and also the limitation of the subthreshold swing (S). As the limitation of subthreshold swing in MOSFET exists, there needs a new device with different carrier mechanism and steeper subthreshold swing are needed.
A steep subthreshold swing allows for lower supply voltage VDD and low power device operation because power scales is the square of VDD. Devices with steeper subthreshold swings behave less gate voltage and give out high ON to OFF currents ratio (ION/IOFF). Therefore, the mainstreams of nowadays technology are higher ION, lower IOFF and lower supply voltage.
To overcome the limitation of subthreshold swing in MOSFET, a new switch with dramatically different carrier injection mechanism needs to be explored. In this work, it explores the Tunnel Field-Effect Transistors (TFET) as an alternative switching device to overcome the fundamental limit of the subthreshold swing in CMOS. TFETs rely on carrier injection via Band-to-Band Tunneling (BTBT) and have the absence of thermal (kT) dependence, which allows for the subthreshold swing to be steeper and less than the value of 60 mV/dec.
Besides new devices and carrier injection mechanism, it will be shown that by employing low bandgap material, Germanium (Ge), only in the source region can be greatly enhanced ON current and ION/IOFF ratio. In addition to Ge source TFET, gate overlaps structure also used in this work to change types of tunneling, from point to line tunneling, in order to have more tunneling area from source to channel. Furthermore, different gate oxide thickness (3～5 nm), spacer thickness (10～20 nm), doping flows (15～45 sccm) and doping concentrations (1E15～5E15 cm-2) are applied in this work to improve Band-to-Band tunneling which induced to higher ON current and ION/IOFF ratio.
From the measured ID-VG or calculated subthreshold swing results of this experimental work, it can conclude that thinner in gate oxide or spacer thickness or high flow rates in doping will result higher ON current and steeper the subthreshold swing. With higher drain voltage, their measured ON current will also be higher. For W/I and W/O gate overlap, the subthreshold swing value with W/I overlap has under 60 mV/dec whereas in W/O overlap has over 60 mV/dec. For ON current, W/I overlap has higher 2 orders than W/O overlap and their ION/IOFF ratio is about 6 orders.

Abstract …………………………………………………………………………… I
摘要 ………………………………………………………………………… III
Acknowledgements …………………………………………………… IV
Table of Contents ………………………………………………… VII
Lists of Figures ………………………………………………… X
Lists of Tables ………………………………………………… XVI
Lists of Symbols ………………………………………………… XVII


CHAPTER 1 MOTIVATION FOR TFET RESEARCH ………… 1
1.1 Introduction ………………………………………… 1
1.2 Power Crisis of CMOS Technology ……… 2
1.3 Requirements for a New Switch …………… 6
1.4 Advantages of TFET Compared to Conventional MOSFET …………………………………………………………………………………………………… 7
1.5 The Proposed Solution to Overcome the Subthreshold Swing …………………………………………………………………………… 8
1.6 Thesis Overview …………………………………………………… 9
References ………………………………………………………… 11


CHAPTER 2 TFET WITH BAND-TO-BAND TUNNELING …… 13
2.1 Introduction ………………………………………………………………… 13
2.2 MOSFET vs. TFET …………………………………………………………… 14
2.2.1 MOSFET Operation ……………………………………………… 15
2.2.2 TFET Operation ……………………………………………… 17
2.3 Device Structure ……………………………………………………… 19
2.4 Working Principle ……………………………………………………… 21
2.5 Energy Band Diagram ………………………………………………… 23
2.6 The Advantages and Disadvantages …………………… 25
2.7 Introduction to Quantum Tunneling ………………… 26
2.7.1 Theory of Tunneling ………………………………… 28
2.7.2 Band-To-Band Tunneling (BTBT) in Diodes ……………… 29
2.8 Lateral and Vertical Tunneling …………………………… 33
2.8.1 Lateral Tunneling ……………………………………… 33
2.8.2 Vertical Tunneling ……………………………………… 34
References …………………………………………………………………………………… 36


CHAPTER 3 PLANAR GERMANIUM SOURCE TFET ………… 44
3.1 Introduction ………………………………………………………………… 44
3.2 The Device Structure and Fundamentals of Ge Source TFET ………………………………………………………………………………………… 44
3.2.1 Impacts of Ge Source on ION / IOFF ……………………………………………………………………………………………………………………… 44
3.2.2 The Operation Principle of Ge Source TFET ……………………………………………………………………………………………………………………… 47
3.2.3 The Advantages of Ge-Source TFET in Comparison with MOSFET …………………………………………………………………… 49
References ………………………………………………………………………………… 50


CHAPTER 4 FABRICATION OF EXPERIMENTAL DEVICE ………………… 52
4.1 Introduction ………………………………………………………………… 52
4.2 Mask Layouts ………………………………………………………………… 52
4.2.1 Device Masks ………………………………………… 52
4.2.2 Test-keys Masks ………………………………………… 55
(A) Contact Resistances …………………………… 55
(B) Channel Conductivity …………………………… 57
(C) Quality of Gate Oxide ………………………… 59
4.3 Experimental Devices …………………………………… 60
4.3.1 Device Parameters and Structures ……… 61
4.3.2 Scaling of Gate Lengths and Widths … 63
4.3.3 Reasons to Split Conditions …………………… 64
4.4 Process Fabrication ……………………………………………………… 68
4.4.1 Overall View in Process Block Diagrams …… 68
4.4.2 Process Flow in Cross Section Views ……… 70
References ……………………………………………………………………………… 84


CHAPTER 5 RESULTS AND DISCUSSIONS …………………………… 85
5.1 Gate Oxide Thickness and Source Materials …… 85
5.2 Spacer Thickness …………………………………………………… 88
5.3 Doping Flow Rates …………………………………………………… 92
5.4 Doping Concentrations ……………………………………………… 95
5.5 With and Without Gate Overlap ………………………… 98


CHAPTER 6 CONCLUSIONS ………………………………………………… 100
6.1 Conclusions of Experiment ……………………………………… 100
6.2 Future Directions of Research …………………………… 101
References …………………………………………………………………………………… 102

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