現今積體電路的設計風格漸漸從二維的複雜設計轉變成一維的規律設計來持續縮小電路的體積，而一維佈局的設計可以用「線+斷點」的方法來實現。一維佈局上隨機分佈的斷點是一維佈局的製造中最主要的挑戰。在這篇論文之
中，我們針對一維佈局的斷點製造提出一個使用定向自組裝及電子束的混合微影流程，同時提出一個斷點重新分配位置的演算法。可以最大化使用定向自組裝製造的斷點數量，並且最小化使用電子束製造的斷點數量。實驗結果顯示，我們提出的演算法是方常快速且有效的。

As the integrated circuit industry continues to scale down the minimun feature size, design style is moving from complex 2D design to highly regular 1D design with the "lines and cuts" process. While dense lines can be fully optimized by their regularity, randomly distributed cuts become a major challenge for the fabrication of 1D layout. In this thesis, we consider a hybrid lithography process combining directed self-assembly (DSA) and E-Beam for 1D gridded layout, and present a cut redistribution algorithm to maximize the number of cuts matched with DSA templates and minimize the number of cuts printed by E-Beam. The robustness of our algorithm is demonstrated through encouraging experimental results.

1 Introduction 1
2 Problem Formulation 4
2.1 Processing
ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Algorithm 7
3.1 Algorithm overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Template matching stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Con
ict graph construction . . . . . . . . . . . . . . . . . . . . . . 8
3.2.2 Cut merging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.3 Template matching . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.4 Iterative renement . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 E-Beam shot selection stage . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Con
ict graph construction . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 E-Beam shot selection . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3 Template renement . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 Experimental Results 19
5 Conclusions 28

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