|
[1] J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach, Springer, 2009. [2] J. Hu, D. Sinha and I. Keller “TAU 2014 contest on removing common path pessimism during timing analysis,” in Proc. ISPD, pp. 153-160, 2014. [3] J. Zejda and P. Frain, “General framework for removal of clock network pessimism,” in Proc. ICCAD, pp. 632-639, 2002. [4] D. Sinha, L. G. Silva, J. Wang, S. Raghunathan, D. Netrabile and A. Shebaita, “TAU 2013 variation aware timing analysis contest,” in Proc. ISPD, pp. 171-178, 2013. [5] D. J. Hathaway, J. P. Alvarez and K. P. Belkhale, “Network timing analysis method which eliminates timing variations between signals traversing a common circuit path,” United States patent 5,636,372 (June 1997). [6] R. Chen , L. Zhang , V. Zolotov , C. Visweswariah and J. Xiong, “Static timing: back to our roots,” Proc. ASPDAC,pp. 310-315, 2008. [7] TAU Contest 2014 on removing common path pessimism, https://sites.google.com/site/taucontest2014/. [8] N. Gupta, “Eliminating pessimism and optimism in timing analysis,” EE Times-India, Oct, 2012. |