隨著現今生產開發流程的縮短，高階合成以及電子系統層級的科技應用已經越來越重要。我們在之前的論文中提出使用通訊控制單元去控制NOC(晶片網路)上封包的傳輸。由於我們有既存的RTL及ESL層級的通訊控制單元設計，我們運用這些設計以不同的方法去實作出高階合成的版本，並且去與手寫的設計所得到的結果作比較。
我們基於RTL版本的例子去實作高階合成設計，這個方法可以得到與手寫RTL完全相同的輸出結果與相當接近的面積。之後我們基於ESL版本的例子去作行為階級的高階合成設計，在這個方法下我們可以利用所提供的函式庫去作通訊介面的合成，但會得到較大的面積結果。
我們同時對如何設定高階合成的細部結構有興趣。因此我們使用了S2Cbench，一個公開的可合成測試設計組。我們從分析不同的細部構造設定結果去找到一些特殊的情形，並且分析其原因以求去找出較佳的細部結構設定。

With the demand of shorter production period today, High-level-synthesis (HLS) and the
electronic-system-level (ESL) technology become more important recently. In our previous
work, we proposed a communication unit for controlling the packet send and receive on the
Network-on-Chip (NOC). Because we have both the RTL and ESL version of this design.
We choose this design and implement to HLS version in dierent method and compare the
result with manual RTL design.
We implement a HLS design base on the manual RTL, which is completely compatible
with the original RTL design after HLS. And then we implement a behavior based HLS
design. We implement this design based on the behavior from ESL design and use a syn-
thesizable interface. We can synthesis the interface to AXI3 with simple bus library. We
both interesting in the micro-architecture setting. The S2Cbench is an open source and
synthesizable SystemC testbench, we choice this testbench to synthesis with dierent micro-
architecture and compare the result. From the analyzing of the dierent micro architecture
result, we nd some special case when certain micro architecture setting. And nding the
reason to explain the special case by observation the information from HLS tool.

1 Introduction 1
1.1 Introduction to High-Level Synthesis . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Existing High-Level Synthesis Research . . . . . . . . . . . . . . . . . . . . . 1
1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 C-to-Silicon Compiler 4
2.1 CtoS Synthesis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 CtoS CDFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 CtoS Area Tree Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Implementation of High-Level Synthesis Communication Unit 8
3.1 Communication Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Data Transmission Protocol . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Synthesizable SystemC Processes . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 RTL Based High-Level-Synthesis Communication Engine . . . . . . . . . . . 17
3.3.1 Synthesis Result of RTL Based High-Level-Synthesis Communication
Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ii
3.4 Behavior Based High-Level-Synthesis Communication Unit with Simple Bus
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 Simple Bus and AXI3 Transactor . . . . . . . . . . . . . . . . . . . . 21
3.4.2 Behavior Based High-Level-Synthesis Communication Unit Architecture 26
3.4.3 Behavior Based High-Level-Synthesis Communication Unit Implemen-
tation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.4 Synthesis Result of Behavior Based High-Level-Synthesis Communica-
tion Unit Implementation . . . . . . . . . . . . . . . . . . . . . . . . 33
4 Exploration of HLS Design 35
4.1 Case study of FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Exploration of Micro Architecture Setting . . . . . . . . . . . . . . . . . . . 37
4.2.1 Design of S2Cbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.2.2 Case studies of Loop Setting . . . . . . . . . . . . . . . . . . . . . . . 38
4.2.3 Case studies of Array Setting . . . . . . . . . . . . . . . . . . . . . . 41
4.2.4 Case study of Function Setting . . . . . . . . . . . . . . . . . . . . . 44
4.3 Characteristic Collation of HLS Coding and Micro-Architecture . . . . . . . 46
4.3.1 Characteristic Collation of HLS Coding . . . . . . . . . . . . . . . . . 46
4.3.2 Characteristic Collation of Micro-Architecture Settings . . . . . . . . 49
5 Conclusion and Future Work 53
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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