隨著製程技術越來越進步，晶片變異（on-chip-variation, OCV）的影響已經佔了時脈偏移(clock skew)相當大的比例，而限制了晶片的效能。為了解決晶片變異的問題，時脈網格(clock mesh)的架構被廣泛的應用在許多高效能的設計上。不幸的是，時脈網格的架構會產生非常大的能量消耗以及瞬間電流。因此，近年來提出了共振時脈(resonant clock)的方法來減少能量消耗問題。然而，先前的方法需要加入大量的去耦電容(decoupling capacitors)，最後的結果常受限於面積成本。在本文中，我們提出了一個創新的時脈共振架構，稱為乒乓網格(Ping-Pong mesh)，來克服那些缺點。我們的兵乓網格架構包含了兩個子網格，分別扮演另一個子網格的去耦電容，且兩個子網格運作在完全相反的時脈相位。我們的兵乓網格有以下兩個優點：（１）兵乓網格不像先前的架構需要額外的去耦電容；（２）相較於先前的架構，兵乓網格能夠減少大約一半的瞬間電流。

List of Contents
List of Contents VI
List of Figures VII
List of Tables VIII
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 PRELIMINARIES 6
CHAPTER 3 IDEAL LC MODEL FOR PING-PONG MESH 8
CHAPTER 4 PING-PONG MESH DESIGN 13
4.1 Mesh Architecture Design 13
4.2 Inductor Implementation 15
4.3 Optimal Inductor Estimation 17
4.4 Inductor Placement 20
CHAPTER 5 EXPERIMENTAL RESULTS 24
CHAPTER 6 CONCLUSIONS 33
REFERENCES 34

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