基於效率高、熱閾值和可擴展性，採用多核心架構，而不是具有較高的頻率單核來實現SoC（系統級晶片）更好的性能是發展的趨勢。
然而，隨著晶片中系統的數量不斷增加，核心間通訊的複雜性急劇增長而設計驗證的難度也越來越高。為了讓多核心架構發揮到最大利益，在平台上運行並行應用程序亦是重要的事情。因此，設計和追蹤與應用程序和硬體協作的驗證是當今的多核系統一個具有挑戰性的問題。

在此論文中，我們提出了一個對多核心平台使用的內嵌式追蹤器架構（通訊追蹤）和專注於跨PE（運算單元）交互應用程式層級的追蹤方法。在應用程式層級追蹤可以提供使用者更有效率的方式找到問題，因為追蹤數據可以被最小化。我們改進了原有的API事件產生器使其具有追蹤存取外部記憶體的功能。此外，晶片網路事件的產生具有更好的效率，如果交易是正常的，便不產生追蹤數據。通訊追蹤包括通訊事件產生器，NoC(晶片網路)事件產生器和追蹤引擎。通訊事件發生器監控PE的傳輸元件而NoC的事件產生器則是監視通過路由器的數據封包。追蹤引擎匯集了來自通訊事件產生器或晶片網路追蹤事件後加上時間戳記，然後壓縮成追蹤數據。

除了之外，我們實作離線分析程式，以幫助使用者分析多核平台上執行的應用程式。使用者可以利用該分析程式增加分析追蹤數據的效率。我們在論文中提出了一些應用程序的通訊追蹤資料的壓縮比可以達到96.01％至99.97％。
通訊事件產生器和追蹤器引擎占整個平台的面積約為1.5% 而NoC事件產生器則是0.57％。

Due to the power efficiency, thermal threshold and scalability, using many-core architecture instead of having a single core with higher frequency to achieve better performance on SoC(System-on-chip) is a trend of the development.
However, when the number of cores in a system is increasing, the complexity of inter-core communication grows rapidly and the difficulty of design verification is also increasing. To get maximum profit of many-core architecture, the parallel application executed on platform is the other important thing. Thus, the verification of design and the debugging cooperating with application and hardware is a challenging issue for many-core systems in nowadays.

In the thesis, we present an embedded debug and trace platform( Communication Tracer) and the methodology for application-level that focus on the interaction of inter-PE( Processing Element) on many-core platform. Debugging and Tracing at application-level can offer user an efficiency way to find the problem because the trace data can be minimized. We improve the original API Event Generator to have the feature of tracing external memory access. Moreover, the NoC Event Generator has better efficiency that if the transaction is normal, there are no trace data generated. The Communication Tracer consists of Communication Event Generator, NoC Event Generator and Tracer Engine. Communication Event Generator monitors the communication of PE and NoC Event Generator monitors the packets that pass through the switch node. Tracer Engine gathers the trace event from Communication Event Generator or NoC Event Generator, appends time stamp and then compressing the trace data.

Moreover, we implement off-line analyzer to help user to profiling the application executed on many-core platform. User can exploit the software application's efficiency by the off-line analyzer extracts and analyze the trace data log from our proposed Communication Tracer. We present some application as cases in this thesis. The compression ratio of trace data in the proposed communication tracer can achieve between 96.01% to 99.97% depended on various cases.
The Communication Event Generator and Tracer Engine is 1.5% of the whole platform and the NoC Event Generator is 0.57% of the whole platform.

1 Introduction
1.1 Introduction of SoC Tracing and Debugging
1.2 The Challenge of Tracing and Debugging on Many-Core SoC
1.3 Motivation and Contribution
1.4 Organization of the Thesis
2 Previous Work
2.1 Background
2.1.1 SystemC
2.1.2 OSCI TLM-2.0
2.1.3 OpenRISC
2.1.4 Bus Protocol
2.1.4.1 Wishbone
2.1.4.2 Open Core Protocol
2.2 Overview of Existent Many-Core Platform
2.2.1 Processing Element
2.2.2 Communication Unit
2.2.3 Network on Chip
2.2.3.1 Arteris NoC(RTL)
2.2.3.2 Transaction Generator 2(ESL)
2.3 Software Communication Library
2.3.1 On-chip Communication Library
2.3.2 iLib Libary
2.4 Overview of Previous Many-Core Tracer
2.4.1 Application-Level Transaction-Based Trace Infrastructure for NoC-Based Many-Core Platform
2.4.2 Transaction-Level Embedded Tracer on Many-Core Platform
2.4.2.1 API Event Generator
2.4.2.2 NoC Transaction Generator
2.5 Existent Method for Tracing and Debugging
3 Component of Proposed Communication Tracer and Implementation 41
3.1 Overview of Communication Tracer
3.2 Communication Event Generator
3.2.1 FSM of Communication Event Generator
3.2.2 Communication Event List
3.3 NoC Event Generator
3.3.1 The Top View of NoC Event Generator
3.3.2 Packet Congested Event Generator
3.3.2.1 Size of Trace FIFO and Dedicated Counter
3.3.2.2 Push Mechanism of Trace FIFO
3.3.2.3 Pop Mechanism of Trace FIFO
3.3.2.4 Packet Congested Event Generator On ESL platform
3.3.3 Hop Count Event Generator
3.3.3.1 Definition of Hop Count
3.3.3.2 Architecture of Hop Count Event Generator
3.4 Tracer Engine
3.4.1 Event Filter
3.4.2 Time Event Generator
3.4.3 Trace Packet Generator
3.4.4 Tracer Control Unit
3.5 Tracer Timer
3.6 Non-Blocking Communication Engine Issue
4 Proposed Tracing and Debugging Methodology and Demonstrations
4.1 The Debugging and Tracing Flow on Many-Core Platform
4.2 Off-line Analyzer
4.2.1 Definition of Communication Time
4.2.2 NAck Related Analsis
4.2.3 Packets Congested on NoC Related
4.2.4 Auto-Paring of Send and Receive
4.3 Simulation Model for Application-Level Debugging and Tracing
4.4 Case Study
4.4.1 Odd-Even Sort
4.4.1.1 Introduction of Odd-Even Sort
4.4.1.2 Cases of Odd-Event Sort
4.4.1.3 Result of Analysis
4.4.2 3 phases of Send and Receive
4.4.2.1 Introduction of 3 phases of Send and Receive
4.4.2.2 Introduction of Barrier Function
4.4.2.3 Cases of 3 phases of Send and Receive
4.4.2.4 Result of Analysis
4.4.3 3D Parallel Graphic Pipeline Program
4.4.3.1 Introduction of 3D Parallel Graphic Pipeline Program
4.4.3.2 The Method of Load Balance
4.4.3.3 Cases of 3D Parallel Graphic Pipeline Program
4.4.3.4 Result of Analysis
4.4.4 Router Decision Bug
5 Experiment Result and Analysis
5.1 The Compression Rate of Communication Trace Data
5.2 The Amount of NoC Trace Data
5.3 The Rate of Generating Trace Data
5.3.1 Analyze the Profling of Switches' Utilization Ratio
5.4 Synthesis Result
6 Conclusion and Future Work
6.1 Conclusion
6.2 Future Work
Appendices
Appendix .A ESL Global Addressing Space on Many-Core Platform
Appendix .B Communication Unit Addressing Space Used in A Processing Element

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