隨著晶片網路複雜度的增加，設計空間探索變得更加的困難。因此，軌跡式模擬器所能提供的模擬速度在設計空間探索當中是不可或缺的。然而，軌跡式模擬所產生的時序卻常常與實際情形相去甚遠，主要原因是在傳統的軌跡式模擬當中，時序是固定的，也無法基於模擬結果做動態的調節。具有處理相依性軌跡的軌跡式模擬器可以解決這個問題，但是這樣的模擬器需要緊密的連結輸入的軌跡，而許多傳統的模擬器以批次的方式模擬軌跡，若要達到上述的目的則必須對模擬器做許多更改及了解。
這篇論文以一個迴路的方式解決這個問題，除了輸入軌跡格式外，不需要對模擬器有多餘的修正或了解，我們使用此方法模擬晶片系統網路，最高可以達到28.75%的精準度增進，相較於全系統模擬器也只有平均3.73%的誤差。

The raising complexity of system architectures makes it more difficult to exploit the design space. For design space exploitation, trace-driven simulation is becoming indispensable due to its simplicity and speed. Unfortunately, the timing produced by trace-driven simulation is often inaccurate by a large margin. This is because the event timing in traditional trace-driven simulators is fixed and cannot be adjusted dynamically according to results out of the simulators. Dependency-aware simulators solve the accuracy problem, but they require close interactions between the input traces and the simulators. Many traditional simulators process trace events in batch, which require non-negligible modification efforts to make them interactive. This thesis solves the problem by adopting an iterative strategy. There is no need to modify the simulators, except perhaps in reading and reformatting the input traces. Our evaluations using Gem5 and BookSim for Network-on-Chip (NoC) simulation show that this technique can achieve up to 28.75% improvement in timing accuracy compared to the traditional trace-driven simulators, and result in only 3.73% error in average in terms of network latency compared to full-system simulators.

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