|
[1] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, B, “Demystifying 3D ICs: The pros and cons of going vertical,” Design and Test of Computers, IEEE, vol.22, Iss.3, pp.498-510, 2005 [2] C. S. Tan, Ronald J. Gutmann, and L. Rafael Reif, “Wafer Level 3-D ICs Process Technology,” Springer, 2008 [3] S. Pasricha, “Exploring Serial Vertical Interconnects for 3D IC,” Design Automation Conference, pp.581-586, 2009 [4] K. Tu, “Reliability challenges in 3D IC packaging technology,” Microelectronics Reliability, vol.51, pp.517-523, 2011 [5] T. Song, C. Liu, D. H. Kim, S. K. Lim, J. Cho, J. Kim, J. S. Pak, S. Ahn, J. Kim, and K. Yoon, “Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs,” International Symposium on Quality Electronic Design, pp.1-7, 2011 [6] K. Yoon, G. Kim, W. Lee, T. Song, J. Lee, H. Lee, K. Park, and J. Kim, “Modeling and Analysis of Coupling between TSVs, Metal, and RDL interconnects in TSV-based 3D IC with Silicon Interposer,” Electronics Packaging Technology Conference, pp.702-706, 2009 [7] R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L.-R. Zheng, “Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits,” IEEE International 3D System Integration Conference, pp.1-8, 2009 [8] C. Liu, T. Song, J. Cho, J. Kim, J. Kim, and S. K. Lim, “Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC,” Design Automation Conference, pp.783-788, 2011 [9] T. Song, C. Liu, Y. Peng, and S. K. Lim, “Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs,” Design Automation Conference, pp.1-7, 2013 [10] T. Xiao, M. Marek-Sadowska, “Crosstalk Reduction by Transistor Sizing,” in Proceedings of Asia and South Pacific Design Automation Conference, pp.137-140, 1999 [11] Y. Y. Chang, Y. C. Huang, V. Narayanan, and C. T. King, “ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise,” in Proceedings of Asia and South Pacific Design Automation Conference, pp.675-680, 2013 [12] R. Kumar and S. P. Khatri, “Crosstalk avoidance codes for 3D VLSI,” Design, Automation and Test in Europe, pp.1673-1678, 2013 [13] Q. Zou, D. Niu, Y. Cao, Y. Xie, “3DLAT: TSV-Based 3D ICs Crosstalk Minimization Utilizing LessAdjacent Transition Code,” in Proceedings of Asia and South Pacific Design Automation Conference, pp.762-767, 2014 [14] Predictive Technology Model. http://ptm.asu.edu/ [15] J. Cho, E. Song, K. Yoon, J. S. Pak, J. Kim, W. Lee, T. Song, K. Kim, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, J. Kim, “Modeling and Analysis of Through- Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring,” Components, Packaging and Manufacturing Technology, IEEE Transactions, vol.1, Iss.2, pp.220-233, 2011 [16] Nangate Open Cell Library. http://www.nangate.com/ [17] M. C. Tsai, T. C. Wang, T. T. Hwang, “Through-Silicon Via Planning in 3-D Floorplanning,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions, vol.19, Iss.8, pp.1448-1457, 2011 [18] GLPK. http://www.gnu.org/software/glpk/ [19] Dummy variable regression. http://www.sagepub.com/upm-data/21120 Chapter 7.pdf |